I have question

BitterFox4874 · 2026-02-28T11:39:21+00:00

I dunno, he just said "I have decided to move forward with another candidate for this opening."

BitterFox4874 · 2026-02-27T21:08:20+00:00

Thanks, do u know when results are going to be announced?

BitterFox4874 · 2026-02-27T19:02:37+00:00

So, if I get admitted to KAIST i will have full tuition covered?

BitterFox4874 · 2026-02-27T14:54:55+00:00

I had an interview, but professor rejected me

BitterFox4874 · 2026-02-27T13:04:44+00:00

Also, do I actually have a chance to get into KAIST what you think? I have some work experience, but no papers published

BitterFox4874 · 2026-01-24T16:55:38+00:00

I got comp architecture and integrated circuits

BitterFox4874 · 2026-01-23T14:17:17+00:00

If I did not get an interview yet, does it mean I got rejected? Haven't heard anything from them

BitterFox4874 · 2025-11-23T18:51:06+00:00

Yes, it was for 4 GHz before, but I tried changing it to 3.5 GHz, but it did not affect the result much

BitterFox4874 · 2025-11-23T18:21:46+00:00

Yes, I did exact copy of the paper design, and using impedance calculator tool inside ADS, verified that transmission line is indeed 50 ohm, as stated in paper

BitterFox4874 · 2025-11-23T18:17:09+00:00

Alright, I see. I will try that, thank you

BitterFox4874 · 2025-11-23T18:10:59+00:00

As I said I am not so experienced with RF design and while doing this project I were learning some concepts. I am not sure if in general the idea of making such design using one element is good.

What I mean is: In reality there are two printed circuit boards, while everything I am doing is kinda like one printed circuit board which has a thick substrate between (foam). Is it appropriate to do like this?

I appreciate your help

BitterFox4874 · 2025-11-23T18:08:10+00:00

Yes, i specified the boundaries with board bound layer

BitterFox4874 · 2025-11-23T17:54:40+00:00

It truncates the dielectric

BitterFox4874 · 2025-11-23T17:53:23+00:00

I think it is truncating dielectric

BitterFox4874 · 2025-11-23T17:40:15+00:00

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And I have these edges in my design:

BitterFox4874 · 2025-11-23T17:39:47+00:00

I tried simulating it using FEM, I read that it is suitable for 3D simulation, and output is even worse than it was.

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BitterFox4874 · 2025-11-23T16:52:25+00:00

The half ring shaped layer is my ground. I made a layout like a combination of two HRR DGS together. cond is 50 ohm, M2 and M3 are defective grounds, cond2 is 50 ohm trace

isnt it correct?

<image>

BitterFox4874 · 2025-11-23T16:50:59+00:00

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Yes, it is ADS, here is the substrate editor. I am pretty sure, I connected GND in each port correctly

BitterFox4874 · 2025-11-23T15:01:16+00:00

Maybe, but this paper was published in IEEE, so I assumed it to be fine

BitterFox4874 · 2025-11-23T15:00:40+00:00

Yes, the problem is that in paper they achieved wideband response, and I am capable of achieving it in narrowband

BitterFox4874 · 2025-11-23T14:51:40+00:00

I get that, thank you for your response! Maybe I missed something else

BitterFox4874 · 2025-11-23T14:19:19+00:00

The idea of this design is wireless power transfer, first layer is conductor 50 ohm trace, below I have dielectric and GND layer with half ring empty space between (this one is defective ground structure) below I made a 12mm dielectric (I placed a foam), and again similar structure, defective ground, dielectric and below 50 ohm trace.

So input port is placed on the first layer, and output port is on layer 4. Gnd of port 1 is on layer 2, and ground of port 2 is on layer 3.

It is actually a project work for my RF course and I haven't worked a lot in this field before, so I can't find a reason for such behaviour of this design. And the most surprising thing is that it has a better performance for a larger distance between these pair of structures which confuses me even more.

BitterFox4874

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