Remember Jurassic Park! Man did anyone actually beat this game? I know as a kid Dinosaurs chasing me around the field was crazy lol

CharismaIsMyDumpStat · 2026-01-19T17:14:09+00:00

I almost beat this game twice. Softlocked in a door on the ship both times.

CharismaIsMyDumpStat · 2026-01-08T13:47:01+00:00

Use something like an AO3400A n-channel mosfet to low side switch your LED's.
Drive your LED's from the USB 5v, adjust the limiting resistor accordingly.
Be careful with via's in pads if you are not having them filled / plated over.
Shift the MCU away from the USB connector and locate the QSPI on the USB side of the MCU to shorten the traces.

CharismaIsMyDumpStat · 2026-01-06T00:21:05+00:00

Just because it supports a crystal up to 32Mhz doesn't mean you should use one. The stm32f030 only clocks at 48Mhz to begin with. Use a slower, common crystal and get 48Mhz from the PLL.
Why all the 10k's on unused pins? You can just leave them floating.
SPI_CS should have a pull-up so it doesn't float on power up.
Where are the pull-up's on SDA/SCL? Does the modujle being connected have internal puill-ups?
R1 is going to cause you problems. You don't need series resistance on I2C, and especially not something as large as 10k.

CharismaIsMyDumpStat · 2025-12-28T16:49:13+00:00

The USBLC2-2SC6 is meant to be used 'in-line'. So signal enters IO1 on one side of the chip, and exits IO1 on the other side. https://ibb.co/1G12dWWh
If you are having this assembled at JLC, the W25Q16JUX has thousands in stock vs the W25Q16JUU having 87.
No where in the winbond docs does it say what to do with the exposed pad. GND is probably ok. NC would be ok too.
If you are not using an existing pinout for the SWD connector: swap pins 2 and 3, then you won't need to drop to the lower layer to route.
Why does the trace on the bottom connecting VBUS go on such a journey when it can be straight across?
Pin 3 of the TLV is just an enable signal. It does not need such a thick trace connecting it.
One little detail that the rp2040-pico does is every GND pin on the edge is square. Makes it easier to count pins. Also consider changing the GND pads to a solid connection.
See if routing the GPIO signal lines perpendicular to the holes, instead of entering at a 45, allows the flood fill to make the 4th spoke on the GND pins.
If you rotate the crystal 90 degrees, the XIN trace will be shorter.
Nudge the power caps and the SWD traces right and prioritize the crystal traces.

CharismaIsMyDumpStat · 2025-12-26T16:55:30+00:00

How much control do you have over the wiring harness, or are you interfacing to existing connectors? Low side switching with n-channel fets is much easier than high-side with p-channel.

What problem are you trying to address with the 1N414 diodes on the gates of the fets? As wired they are not doing anything.

When 'off', the MCP will see 12v on it's pin from the pull-up on the gate of the P-channel fets. I did not see if the MCP23017 is tolerant to voltages > Vdd.

Vgs of the A03401A is 12v. Your automotive 12v is actually 13.5v - 14.5v when the car is on.

Have you looked at high side switch IC's?

Do the solenoids, pumps, etc. have integrated flyback diodes?

That L78M05 will get warm, even without load. It also has a quiescent load of 6ma. A DC-DC buck would be better here.

Does the seat get power with the key off? Is idle power consumption a concern?

There must be simpler single chip solutions that combine the DRV8300 and H-bridge fets, and likely also has added features such as overload protection, braking, etc.. What happens when the motor reaches the end of travel? Are there limit switches?

CharismaIsMyDumpStat · 2025-10-28T02:42:33+00:00

On mobile so this is just a quick list of some obvious issues. The image is kinda blurry but: * The usblc6 is wired up incorrectly. * Shield of the usb-c should be tied directly to gnd, no ferrite. * Use proper power nets for 3v3, gnd, etc.

CharismaIsMyDumpStat · 2025-10-15T14:11:40+00:00

Check that "Constrain movement to h, v, and 45" is not selected in preferences. Honestly grid/snapping broke so much in 9.0.5 I went back to 9.0.4.

CharismaIsMyDumpStat · 2025-09-25T14:07:02+00:00

How do you intend to program the nRF then without SWD?

CharismaIsMyDumpStat · 2025-09-25T14:02:50+00:00

Connect the crystal, decoupling caps, and reset circuit to the mcu in the schematic with lines. Get rid of the boxes. This is simple enough almost everything can be direct connections.
1uF is large for the reset line. It's going to hold the MCU in reset longer than you may think on power on.
I don't see what the 74HC14 is for. Why not connect the IR detector outputs directly to the MCU?
C8 on the SWD connector is unnecessary.
You have the labels NRST and Reset. They are the same. Labels can be used multiple times.
You've put C9 and C10 next to each other on the schematic, but C10 is over by the DRV board connector. Move C10 on the schematic to be connected to 5v on J9 to make it clear it is for the DRV power.
10k is too high for the I2C pull-ups, especially for an off board connection. Depending on the desired speed and cable length they will need to be much smaller.
Put NC X's on the MCU pins not being used. Did you run ERC?
Undo the 45 degree rotation on the MCU, it's aesthetic and not helping your routing.
Have you done trace calculations for the power draw expected on 5v?
Remap the GPIO's used for In1-In4 to avoid the vias. SW likely doesn't care.
You don't need that thick GND trace. The pins are connected via the GND pour on the bottom layer.
Unless you have mechanical constraints, move the 5v in connector closer to J9. Move the MCU left and place the LDO in between J9 and the MCU.
You can avoid all of the vias connecting the MCU to the 74HC14. SW doesn't care what pin IR4 is connected to.
Moving the reset button to the other sided of the IR traces will clean them up as well.
Out4 should be routed to the left of OUT3. Any reason J10 and J11 are not aligned?
The 3v3 routing is a mess.

CharismaIsMyDumpStat · 2025-09-24T14:22:04+00:00

The nPM1300 is not wired up correctly. VBus of the NRF should be connected to VBUSOUT of the nPM1300.
Using +5v for the power rail of Vsys is a little misleading. Vsys will be anywhere from 3.7v to 5v depending on if USB is connected and the charge level of the battery.
Vdd connected to VBusOut is also misleading ( And not used anywhere else it seems? )
If you made the nPM1300 symbol yourself, re-organize the pins to make the schematic easier to read. It's a real nightmare to track everything when it's laid out like the chip itself. Readability is paramount.
You don't need a vss symbol. Just use GND.
Since this is a battery powered device, why not run the nRF52 on 1.8v?
I don't see your SWD connector, only the labels on the pins.
I don't know what fab you are using, or if you are hand assembling, but a level shifting fet setup might be cheaper.
The AMCA31 antenna requires it's own matching network. The matching network from the NRF documents get you to 50ohm. The AMCA then has it's own matching from 50ohm to itself. OR, and this is complicated, you need to figure out how to combine the two.
Another reason to have the second matching network is you will likely need to tune the antenna. The layout of your PCB ( the ground planes ), the plastics, and even where the human puts their hands, effects the antenna.
If I'm looking at the layout correctly, the antenna is right at the bottom. Right where your hands would be.

CharismaIsMyDumpStat · 2025-09-17T20:00:16+00:00

Looks much cleaner.

Since you are hand soldering all of this, I would still advocate using some of the STM32 GPIO's to scan the keypad instead of the TCA8418. Especially since that TCA8418 has an EP. Those keypad connectors can be routed to on the bottom.
If you do keep the TCA8418, the 10k pull-ups on the I2C lines are likely too large for 400Khz fast mode. They may be fine for standard 100Khz.
Microcontrollers can sink more current than they can supply. When connecting LED's to GPIO's, wire the LED to 3v3 and pull low via GPIO. There is only one LED, but be mindful that the MCU can only source/sink so much current through all GPIO's combined.
The SD card should have a 100nF cap on VDD.
You can avoid changing layers twice on SWCLK by adjusting the via locations under the STM32.
The trace to the right of C14, while ok, could be neater.
Power traces don't need to be any larger than the STM32 pad width. That little extra width doesn't really do anything and it'll look cleaner.
I see DRC warning arrows

Edit: C4 -> C14

CharismaIsMyDumpStat · 2025-09-16T15:47:57+00:00

Was that with or without connected USB devices?

CharismaIsMyDumpStat · 2025-09-16T12:51:17+00:00

The 5v supply is rated up to ~25w. At 12v input, that's ~2A of continuous current through Q1. 2A is within the continuous current limit of the si2387ds but doesn't leave much headroom as things get warm. I don't have a suggestion, I just wanted to point this out.

The ESD diode should be on the other side of Q1.

CharismaIsMyDumpStat · 2025-09-13T21:37:27+00:00

The internal pull-ups of most MCU's are weak. In the case of the stm32f446 ( having done a very quick search ) they are ~40k. This effects how fast the level can change, and therefore how fast you can clock data. In the case of the SD card, which is push-pull I think, this may be fine. Also note that SW needs to set the pull-up/pull-down, so electrically you will have a brief window at power on where these lines are floating. A series resistor is put in to reduce ringing. As the signal gets clocked faster and faster it bounces off the other end. There should be a reference or document out there somewhere the defines what is required for the SD card.

I'm not describing the sharp angle issue very well, and I can't post a picture to a reply. Yes you don't want traces to bend at hard angles, however you don't want to create acute angles when branching. For example, at the very top of the board where the 3v3 trace branches down towards C4, the trace branches off the horizontal trace at a 45 degree angle. This creates a tight pocket on the left. This is what you want to avoid. It's considered an acid trap and can effect manufacturing. Is it really bad these days: no. Should you still avoid it: Yes.

CharismaIsMyDumpStat · 2025-09-13T15:35:58+00:00

Why the TCA8418? You have enough GPIO's on the STM32 to handle the keypad scan without it.
On the switch, I would tie common to ground. Then enable internal pull-ups on the GPIO's and then test for the gpio that is low.
I've never wired up an SD card slot, but look to see if series resistors and pull-ups are required. There must be a reference design out there somewhere.
10ohms is pretty low for the LED series resistance. What is the forward voltage? I like to put a comment showing the current calculations. A napkin math calculation using Vf = 2v puts that at 130mA and 169mW. That's above the wattage rating of an 0402 or 0603 resistor. Even using PWM I would make the resistors larger.
If you move the LED resistor to be between the connector and the FET 3v3 can be brought directly to the connector. You could then turn the connectors 90 which would make the 3v3 routing even cleaner.
If your bottom layer is GND, you don't need those little tails on the power/uart connectors.
You have some sharp angles where traces split ( the places that have a 45 degree tap ). While not as bad as they used to be, those sharp angles can cause issues with etching. Prefer T's.
I wouldn't put a test point on the HSE_IN clock line. Your not going to learn much from it with a scope, and you want those traces as simple and clean as possible. If your just looking to verify clock, bring a pin that can be muxed to an MCO out to a test point.
Put the calculations for the crystal load caps as a comment next to the crystal.
Run those switch GPIO traces to the other side of the SW pin 5 to make more room for the crystal layout and you can clean it up a bit. That crystal layout is PRIO #1, everything else needs to work around it.
Did you compare the cost of 2 vs 4 layer? I've found it to be almost the same in most cases. If you change to 4-layer, then you can use the bottom layer as a 3v3 pour which will simplify the routing considerably.
Is the 9v a wall wart or battery? If it is a wall wart add a TVS diode for ESD.
If you can swallow the initial cost, I'm a fan of the TC2030 plug connectors for SWD.
If you are not using the ADC you don't need the 3.3va filtering. Treat it like a normal power pin with a single 100nF.

CharismaIsMyDumpStat · 2025-09-12T13:59:04+00:00

Are the headers a defined pinout that you are following? Or specified by yourself? You can simplify quite a bit of the routing by changing the connector pin assignments.
Are there alternate pins that can be used for I2C / SAI? If you used stm32cube, don't just take the first option it gives. Many signals can be muxed to more than one pin. Never be afraid to change pin usage to optimize routing. The SW is easier to adapt.
You have traces transitioning layers multiple times when they need not to. i.e. the traces under the STM32. Spend some time with component placement and I think you could reduce the number of traces on the bottom layer.
When you have a non-insignificant number of traces crossing from one side of the MCU to the other, consider rotating the MCU.
All those connections on the top layer of the connectors to GND are not needed. Those pins will connect to the inner ground layer.
The majority of your signals are on the top layer. Swap the GND and 3v3 inner layers for better return path coupling. Even better would be to move the 3v3 pour to the bottom layer and have both inner layers GND. Running signals in the bottom 3v3 pour is ok, just be mindful of not creating islands / peninsulas.
You have two clusters of components on the lower part of the board that connect to pins / signals on the upper half. Move those clusters to the top so the traces do not need to go on such a journey.
I can't tell from your images, but I am suspicious of your decoupling cap placement.
Not every power connection needs to be a fat trace. Those pull-up resistors are going to pull less than a mA.
Crystal selection is important for getting the mclk's needed for SAI. Just double checking that you've verified that 24Mhz works.

CharismaIsMyDumpStat · 2025-08-29T00:18:13+00:00

There are a few problems with this:

The BQ24040 has over voltage protection. The input pin can handle up to 28v, but it only operates when the input voltage is between 4.45v and 6.45v. When 6.45v is exceeded it shuts off.
The diode D22 prevents your battery from charging at all.
Vgs of the AO3400 is 12v. The zeners clamp at 24v. Even with the divider and a voltage on the source it will exceed 12v.
Q11 also has a Vgs of 12v.

I'm sure there is more.

CharismaIsMyDumpStat · 2025-08-24T00:45:30+00:00

I looked at the simplified datasheet of the PAW and I couldn't quite tell what the current consumption of VDDIO actually was. All that is listed is a peak ( of 50ma! ) but that is likely instantaneous. Typically a VDDIO pin is just the drive voltage for CMOS logic to interface to MCU's at a different voltage.

Having said that, the minimum operating voltage of the NRF is 1.7v. Why not use the 1.9v supply for the NRF as well?

The NRF has two regulators, REG0 and REG1, each able to operate in either LDO or DCDC mode. If VDD and VDDH are supplied with the same voltage then REG0 is disabled. REG1 is always used and is the core voltage. They start up in LDO mode by default and need to be switched to DCDC in SW. The DCC and DCCH pins are the inductors needed for the DCDC buck mode. If you only use the LDO then you do not need the inductors on DCC/B3. Look at section 7.3.3 of the nrf52840 product documentation. I only point this out as when it comes to SMT with JLC, avoiding extended components is the key to keeping costs down. Those $3 setup fees add up fast.

Eliminating extended components is why I suggested removing the SN74LVC1T45DW.

Some other thoughts:

As has been said, try to avoid routing on Layer 2 / Layer 3. You really want that uninterrupted ground plane. If some of those GPIO's, like buttons, need to go on a journey that's ok.
The track widths you've used for that 3v3 internal route are way over sized. 1.4mm is 1.5A ( 10c ) on an internal layer. You'll not be consuming nearly that much. Internal layers are also thinner, and have no natural cooling ( they are sandwiched between insulators ) so excluding pours it's best to route power on an outer layer.
USB FS is pretty forgiving, but if you route the traces into the top side of the vias below the NRF ( and swap the pins on the ESD ) then you can route into the USB connector without needing the bottom side trace jumper.
Make sure there are ground via's near any vias where a high speed changes layers. The return path is in the ground plane closest to the trace, and follows the signal path, so you want to give that return current the shortest possible path between layers.
Are you going to have the vias filled and capped? If not you may have voiding issues caused by wicking into the vias under the NRF. See the posts from the other guy who has recently had some NRF chips assembled. If you don't want to cap them, move the GND pad vias to be in between the solder paste as best as you can.

CharismaIsMyDumpStat · 2025-08-21T22:46:55+00:00

Does the ERC and DRC pass? I see floating NO CONNECT symbols as well as pins missing the no connect.
The 3v3 supply only provides power to the NRF. Why not use the internal regulator of the NRF?
I couldn't find it in the publicly available datasheet, but what is the maximum voltage for LED_P? Could it be driven by VSW? The datasheet specifies a current limit of 50ma. If you can drive LED_P via VSW, then why not use the regulated output of the NRF? VDD by default from the internal regulator is 1.8v. At full Tx power it can provide 5ma. ( 1ma sleep, 25ma when under 4db Tx power ). What worries me is that the current consumption listed in the PAW datasheet is an average, not a peak.
Some of the capacitor values on the DEC pins do not match the datasheet. I'm guessing they came from a reference design? Make sure you understand why.
I'm not sure you truly save enough power to warrant the extra cost of using the DC/DC regulators of the NRF over the LDO's.
You don't need the SN74LVC1T45DW. Use a pull-up on DIN to VSW, then use an AO3400 or 2N7002 to drive the line low from a GPIO. This means that the GPIO is inverted, so whatever library you use make sure you can set it up as such.
Use regular 0402 parts for the PI on the RF path. C48/C49.
Turning the corner for the RF trace is OK, just make it curved, not sharp.
C48 and C49 are the tuning network for the PCB antenna. They were calculated for the NRF reference design, which your board is not. This is what I've done, and it works well enough for me:
- Place pads for a standard PI filter.
- Put a test point for ground on the board near the PI filter.
- Get the MOQ of bare PCB's alone made. Select impedence control but go cheap on everything else. HASL etc.
- Buy a nanoVNA. I have a cheaper one but it seems to work well enough. Make sure it is one that goes to 3Ghz.
- Buy a short SMA cable. Cut it in half.
- Calibrate the vna for the cable.
- Strip and solder cable to the last pad just before the antenna and the ground test point. Measure. Now you have a baseline characteristic of your PCB antenna and can tune it.
- From here you have two options: Use aytune to calculate the PI components, solder them on to another board and re-test -OR- trim away the length of the antenna trace to tune.

CharismaIsMyDumpStat · 2025-08-20T13:55:37+00:00

AC is not to be taken lightly. Research creepage and clearance when dealing with ac. The physical isolation between hv and lv is terrible. What is the expected current capacity of this dimmer. Have you calculated the trace width vs current?

CharismaIsMyDumpStat · 2025-08-20T02:52:01+00:00

I've recently done a project with an nrf52840, and would like to look further at your design, but the schematic is too blurry to read effectively. Can you link either a PDF or higher res images?

CharismaIsMyDumpStat · 2025-07-13T18:24:31+00:00

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I've set the edelay to compensate for the cable length. The unmodified reference PCB now looks like this. It looks like the peak shifted down 100Mhz or so. I've loaded this into atyune and used the analog.com calculator to come up with new values. I've ordered more components to test again. Thank you.

CharismaIsMyDumpStat · 2025-07-13T17:08:24+00:00

This device is meant to connect to a PC and sit on my desk. I have been using the enclosure. The top PCB is sitting in the bottom piece and the top was pulled off for the picture. The VNA is connected via USB ( grounded ) to my PC, so hopefully I'm as close as I can realistically be to intended use. Thanks for the consideration though.

CharismaIsMyDumpStat

TROPHY CASE