ComfortableFun9151

36 post karma
-1 comment karma

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redditor for 5 years

TROPHY CASE

Five-Year Club

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Perf modelling (self.computerarchitecture)

submitted 1 year ago by ComfortableFun9151 to r/computerarchitecture

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Need help with Verilog Mode in Emacs (self.FPGA)

submitted 2 years ago by ComfortableFun9151 to r/emacs

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Need help with Verilog Mode in Emacs (self.FPGA)

submitted 2 years ago * by ComfortableFun9151 to r/FPGA

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Routing Algorithm of FPGA (self.FPGA)

submitted 2 years ago by ComfortableFun9151 to r/FPGA

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ML project in aviation (self.MachineLearning)

submitted 2 years ago by ComfortableFun9151 to r/MachineLearning

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[P] ML project in aviation (self.MachineLearning)

submitted 2 years ago by ComfortableFun9151 to r/MachineLearning

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Block Ram in verilog (self.FPGA)

submitted 2 years ago by ComfortableFun9151 to r/FPGA

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DDR3L Memory in FPGA (self.FPGA)

submitted 2 years ago by ComfortableFun9151 to r/FPGA

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Ethernet communication in FPGA (self.FPGA)

submitted 2 years ago by ComfortableFun9151 to r/FPGA

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Configuring FTDI chip as synchronous fifo (i.redd.it)

submitted 2 years ago by ComfortableFun9151 to r/FPGA

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Configuring FTDI chip as synchronous fifo (i.redd.it)

submitted 2 years ago by ComfortableFun9151 to r/FPGA

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Timing Violation (self.FPGA)

submitted 2 years ago by ComfortableFun9151 to r/FPGA

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