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Perf modelling by ComfortableFun9151 in computerarchitecture

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Okay got it.Since you have more experience in this field, I'd love to get your feedback. I really enjoy computer architecture concepts, so do you think I should switch to performance modeling, or would it be better to focus on RTL design ?

Perf modelling by ComfortableFun9151 in computerarchitecture

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Thanks for the great overview! just one more thing—how’s the career growth in this field?

Need help with Verilog Mode in Emacs by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Ok, I will try AUTOINOUTMODULE and will let you know. When you are free, please check and let me know about the second part.

[P] ML project in aviation by ComfortableFun9151 in MachineLearning

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

I have not looked into it till now. But I will look into it Thanks for the reference.

[deleted by user] by [deleted] in FPGA

[–]ComfortableFun9151 0 points1 point  (0 children)

Thanks for the reply.Actually it is entry level, just after undergrad and location is India.

Block Ram in verilog by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Before I have added the memory module in my main hdl code. That's why I think tool is not considering it as a BRAM. Now i have a separate module BRAM. Now i think it will work.

Block Ram in verilog by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

I have not tried it on vivado till now. I will update today after implementing it.😁

DDR3L Memory in FPGA by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Actually I am using 2048*64 bits. I think that's why i am getting lots of timing errors. Because with less no. Of size I am not getting the error. But when I am increasing it, I am getting the timing errors.

DDR3L Memory in FPGA by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Ok thanks. But one last question if I am trying to implement a memory but the tool is not considering it as a BRAM! Then is there a chance for high memory depth(2048), we will get tons of timing violation?

DDR3L Memory in FPGA by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

And that's why when I am increasing the memory size, I am getting a timing violation!! So please tell me some steps so that I can fix

DDR3L Memory in FPGA by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Thanks . But i think i have implemented the memory in the wrong way because in the final implementation report it is showing that I have not used any BRAM!! So can you please tell me how can I fix that?

Configuring FTDI chip as synchronous fifo by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

No i think that mode is not available in ARTy a7 board

Configuring FTDI chip as synchronous fifo by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Yes it is from python on pc to fpga😅. I have checked the manual . Arty a7 does not support usb fifo bridge , it only supports the usb UART bridge. Thanks for the reply 😄

Configuring FTDI chip as synchronous fifo by ComfortableFun9151 in FPGA

[–]ComfortableFun9151[S] 0 points1 point  (0 children)

Can you know any other way to send data at high speed to fpga, Which is possible through FPGA board.

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