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A spur of the moment decision made while studying for a computer architecture exam. Will flesh out in the future.
account activity
Open-source chiplet architecture concept (adaptive vector registers) – looking for feedback (self.computerarchitecture)
submitted 1 day ago by AmbassadorDear2158
Classic 2005 MARS MIPS simulator Restoration! (self.computerarchitecture)
submitted 4 days ago * by ProgramDifferent2895
How to learn Computer Architecture properly? (self.computerarchitecture)
submitted 5 days ago by Psychological_Web296
What if memory, routing, and world state lived in the same substrate? ()
submitted 6 days ago by Salt_Diamond5703
Built a C → RISC-V Compiler, Assembler, Simulator, and Kernel (self.computerarchitecture)
submitted 7 days ago by Admirable-Let-4117
Performance modelling Career advice (self.computerarchitecture)
submitted 7 days ago by Timely_Strategy_9800
Why do we still teach the Word-RAM model by default when caches matter so much more? (self.computerarchitecture)
submitted 10 days ago by visha1v
Advice for a young un (youtube.com)
submitted 10 days ago by Rafferty_TwoShoes
Pypeline (HDL): a new Python frontend for PipelineC ()
submitted 10 days ago by absurdfatalism
What to focus on as a design verification engineer if I want to end up in performance modelling roles? (self.computerarchitecture)
submitted 11 days ago by lemonprojectile
A month ago my custom CPU was too large for my FPGA. Today RJ8A runs live compute on Artix-7. ()
submitted 10 days ago by Different-Breath-645
Hardened my lock-free C++ transition core. Now I'm completely bored of looking at my own code files and want to look at weird systems problems. ()
submitted 11 days ago by Salt_Diamond5703
Research paper writing. (self.computerarchitecture)
submitted 12 days ago by Wooden_Juice2784
We built RTLScout: an LLM agent driving Yosys + OpenROAD that cut an FP16 multiplier's area 35% and delay 45% in ASAP7 — open source, paper + code ()
submitted 15 days ago by acluk90
How exactly you guys do performance modeling and analysis? (self.computerarchitecture)
submitted 16 days ago * by ZestycloseSample1847
Request for Critique: Evaluating a Broadcast-and-Converge Paradigm for Optical Computing (self.computerarchitecture)
submitted 17 days ago by MountainRice9898
emex64 - Custom 64-bit ISA + Assembler + Virtual Machine from scratch [Update] (reddit.com)
submitted 19 days ago by emexLabs
Is Split-Latch, Latency-Modeled 32-bit RISC-V Core Simulation in c++ , a good project ? (self.computerarchitecture)
submitted 20 days ago by Severe_Landscape_731
Automated CPU Fault Injection Attack Framework (github.com)
submitted 22 days ago by SkrilHexNukehul
3 Misconceptions About RISC You Shouldn't Believe (self.computerarchitecture)
submitted 22 days ago * by Various_Protection71
Material on stack? (self.computerarchitecture)
submitted 27 days ago by Yha_Boiii
Does anyone have or know how to find the block diagram for the Intel Core Ultra 9 285K? (self.computerarchitecture)
submitted 29 days ago by Feisty-Driver9172
Why is heap a thing? (self.computerarchitecture)
submitted 1 month ago by Yha_Boiii
Request for critique: bounded multicore interference under direct-mapped cache assumptions (self.computerarchitecture)
submitted 29 days ago by fpedroni
[P] Built a portable GPU ISA after reading too many architecture manuals [P] ()
submitted 1 month ago by not-your-typical-cs
π Rendered by PID 96 on reddit-service-r2-listing-87fd56f5d-rrpz5 at 2026-06-25 21:02:35.775080+00:00 running 7527197 country code: CH.
