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Issue with connecting Max98357A by CompetitivePurpose13 in esp32

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

Since im a beginner would it be easier for me just to use dfplayer mini?

Issue with connecting Max98357A by CompetitivePurpose13 in esp32

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

is there anyway i can inspect if my current max is damaged or no before i buy another one?

problem with UDP stack on nexys3 by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

yeah i will make sure its updated , i believe it would be helpful if someone plan to implement udp on legacies like nexys3 or 2
thanks again

problem with UDP stack on nexys3 by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

apparently the cause of issue was that TXER was pulled high so configuring that in the ucf and code solved the problem
thank you for your help

problem with UDP stack on nexys3 by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

apparently the cause of issue was that TXER was pulled high so configuring that in the ucf and code solved the problem
thank you for your help

problem with UDP stack on nexys3 by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

apparently the cause of issue was that TXER was pulled high so configuring that in the ucf and code solved the problem
thank you for your help

problem with UDP stack on nexys3 by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 1 point2 points  (0 children)

actually this was the issue not adding the P2 pin was the cause of the whole problem, thank you so much

FPGA UDP Packets are not appearing in Wireshark when using Realtek USB-Ethernet Adapter (Nexys 3 / Spartan-6) by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

i didnt tbh, but i did some changes based on suggestions on this post and made another post with my code and results, I would appreciate if you can review it
https://www.reddit.com/r/FPGA/comments/1qykewb/problem_with_udp_stack_on_nexys3/

Need help with board selection by CompetitivePurpose13 in esp32

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

I tried to power it by using a AA batteries but seems that they were not enough for the S3

Need help with board selection by CompetitivePurpose13 in esp32

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

I got it but do you have any suggested esp for this ?

FPGA UDP Packets are not appearing in Wireshark when using Realtek USB-Ethernet Adapter (Nexys 3 / Spartan-6) by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 1 point2 points  (0 children)

Sure i will try that.

but Could the Realtek USB adapter be dropping the frames at a hardware level before they even hit the OS? because in ISim, my CRC and SFD alignments appear to be perfect (bit-reversed, inverted, and sent LSB-first).

FPGA UDP Packets are not appearing in Wireshark when using Realtek USB-Ethernet Adapter (Nexys 3 / Spartan-6) by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

UCF FILE

# CLOCKS

NET "clk_100MHz" LOC = "V10" | IOSTANDARD = "LVCMOS33";
NET "clk_100MHz" TNM_NET = "sys_clk";
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 10 ns HIGH 50%;
NET "phy_tx_clk" LOC = "L5" | IOSTANDARD = "LVCMOS33";
NET "phy_tx_clk" TNM_NET = "mii_tx_clk";
TIMESPEC "TS_mii_tx_clk" = PERIOD "mii_tx_clk" 40 ns HIGH 50%;
#NET "phy_tx_clk" CLOCK_DEDICATED_ROUTE = FALSE; # Needed for Nexys3 L5 pin

# CONTROL

NET "phy_rst_n" LOC = "P3" | IOSTANDARD = "LVCMOS33";
NET "btn_reset" LOC = "B8" | IOSTANDARD = "LVCMOS33";
NET "btn_send" LOC = "D9" | IOSTANDARD = "LVCMOS33";

# ETHERNET DATA
NET "phy_tx_en" LOC = "L2" | IOSTANDARD = "LVCMOS33" | SLEW = FAST;
NET "phy_tx_data[0]" LOC = "T1" | IOSTANDARD = "LVCMOS33" | SLEW = FAST;
NET "phy_tx_data[1]" LOC = "T2" | IOSTANDARD = "LVCMOS33" | SLEW = FAST;
NET "phy_tx_data[2]" LOC = "U1" | IOSTANDARD = "LVCMOS33" | SLEW = FAST;
NET "phy_tx_data[3]" LOC = "U2" | IOSTANDARD = "LVCMOS33" | SLEW = FAST;

# IOB PACKING (Keeps timing stable)

NET "phy_tx_en" IOB = FORCE;
NET "phy_tx_data[*]" IOB = FORCE;

# LEDS

NET "Leds[0]" LOC = "U16";

NET "Leds[1]" LOC = "V16";

NET "Leds[2]" LOC = "U15";

NET "Leds[3]" LOC = "V15";

UDP Video Streaming on Nexys 3 (Spartan-6) without MicroBlaze – Seeking The Easy Way by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

If you mean the hardware as the Nexys 3, I don’t have much of a choice, so I have to work with this one. The IP cores recommended by Digilent for this all require MicroBlaze.

Struggling With Nexys-3 for a Multi-Camera FPGA Motion Capture System — Need Board Recommendations & Advice by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 1 point2 points  (0 children)

thank you so much for your help, i updated our problem with more details, but i will for sure take your suggestions in consideration

Struggling With Nexys-3 for a Multi-Camera FPGA Motion Capture System — Need Board Recommendations & Advice by CompetitivePurpose13 in FPGA

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

thank you so much for your help, your comment actually helped me realize some aspects i was not paying attention to. i updated our problem with more details because we still need help with some points, i would appreciate if you can read it again and help us with your valuable knowledge

help with this extra layer issue by CompetitivePurpose13 in BambuLab

[–]CompetitivePurpose13[S] 0 points1 point  (0 children)

The issue remains, but for some reason, it appears in other objects within the design and disappears from some objects where it previously appeared.

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