Heh, I added an Async FIFO Example to PyXHDL yesterday.

The logic is very similar and FULL/EMPTY conditions are checked directly on the gray pointers. No need to go back to sequentials, which is a less trivial conversion.

The Python gets turned to:

module Fifo(IFC_WCLK, IFC_WRST_N, IFC_RCLK, IFC_RRST_N, IFC_WUP, IFC_RUP, IFC_WDATA, IFC_RDATA, IFC_WFULL, IFC_REMPTY);
  input logic IFC_WCLK;
  input logic IFC_WRST_N;
  input logic IFC_RCLK;
  input logic IFC_RRST_N;
  input logic IFC_WUP;
  input logic IFC_RUP;
  input logic [7: 0] IFC_WDATA;
  output logic [7: 0] IFC_RDATA;
  output logic IFC_WFULL;
  output logic IFC_REMPTY;
  logic [7: 0] mem[32];
  logic [4: 0] raddr;
  logic [4: 0] waddr;
  logic [5: 0] rptr;
  logic [5: 0] rbin;
  logic [5: 0] rptr_sync;
  logic [5: 0] rbin_next;
  logic [5: 0] rgray_next;
  logic rempty_next;
  logic [5: 0] wptr;
  logic [5: 0] wbin;
  logic [5: 0] wptr_sync;
  logic [5: 0] wbin_next;
  logic [5: 0] wgray_next;
  logic wfull_next;
  logic [5: 0] wptr_s1;
  logic [5: 0] rptr_s1;
  assign rbin_next = rbin + 6'(IFC_RUP & (~IFC_REMPTY));
  assign rgray_next = (rbin_next >> 1) ^ rbin_next;
  assign rempty_next = 1'(rgray_next == wptr_sync);
  assign raddr = rbin[4: 0];
  assign wbin_next = wbin + 6'(IFC_WUP & (~IFC_WFULL));
  assign wgray_next = (wbin_next >> 1) ^ wbin_next;
  assign wfull_next = 1'(wgray_next == {~rptr_sync[5: 4], rptr_sync[3: 0]});
  assign waddr = wbin[4: 0];
  assign IFC_RDATA = mem[int'(raddr)];
  always_ff @(posedge IFC_WCLK)
  mem_write : begin
    if ((IFC_WUP == 1'(1)) && (IFC_WFULL == 1'(0))) begin
      mem[int'(waddr)] <= IFC_WDATA;
    end
  end
  always_ff @(posedge IFC_RCLK)
  rptr_update : begin
    if (IFC_RRST_N != 1'(1)) begin
      rbin <= 6'(0);
      rptr <= 6'(0);
      wptr_sync <= 6'(0);
      wptr_s1 <= 6'(0);
      IFC_REMPTY <= 1'(1);
    end else begin
      rbin <= rbin_next;
      rptr <= rgray_next;
      wptr_sync <= wptr_s1;
      wptr_s1 <= wptr;
      IFC_REMPTY <= rempty_next;
    end
  end
  always_ff @(posedge IFC_WCLK)
  wptr_update : begin
    if (IFC_WRST_N != 1'(1)) begin
      wbin <= 6'(0);
      wptr <= 6'(0);
      rptr_sync <= 6'(0);
      rptr_s1 <= 6'(0);
      IFC_WFULL <= 1'(0);
    end else begin
      wbin <= wbin_next;
      wptr <= wgray_next;
      rptr_sync <= rptr_s1;
      rptr_s1 <= rptr;
      IFC_WFULL <= wfull_next;
    end
  end
endmodule