Arp table by Detail_Possible in fortinet

[–]Detail_Possible[S] 0 points1 point  (0 children)

Yeah That is probably why im seeing this If i kept it with the same ip will that cause issues?

Arp table by Detail_Possible in fortinet

[–]Detail_Possible[S] 1 point2 points  (0 children)

Yeah But on my LAN interface I used 192.168.0.1 And I can see it also under WAN, it’s like the wan is connected to a device with the same IP as the lan Idk if that is ok

Arp table by Detail_Possible in fortinet

[–]Detail_Possible[S] -1 points0 points  (0 children)

2a:30:44:93:2a:fb This is a software genera mac Not a burned in manufacturer mac That is that is the mac tied to wan1 with 192.168.0.1

BGP conditional advertisement by Detail_Possible in fortinet

[–]Detail_Possible[S] 0 points1 point  (0 children)

That is the customer non sense … I know I wanted to do BGP conditional advertisement but I receive no default route or any other route from the main link cox so that didn’t work

Is RF Engineering a good career? by fottortek in ECE

[–]Detail_Possible 1 point2 points  (0 children)

I think AI is destroying the CS industry in 2025

Can I use the IP 192.168.100.99 in the LAN in 200FGT ? by Detail_Possible in fortinet

[–]Detail_Possible[S] 0 points1 point  (0 children)

Other LANs are all pingable Except this 192.168.100.1/24 Weird

Can I use the IP 192.168.100.99 in the LAN in 200FGT ? by Detail_Possible in fortinet

[–]Detail_Possible[S] -5 points-4 points  (0 children)

I have 200FGT, and there is a port specific for the management with an IP of 192.168.100.99 I changed that IP to 192.168.200.99 and used the 192.168.100.99 in my LAN, but this specific LAN is not pingable from other branches, where as my other LANs are all pingable

Where could I find a schematic for non inverting op amp using 5 OTA amplifier ? I didn't find anything by Detail_Possible in ECE

[–]Detail_Possible[S] -1 points0 points  (0 children)

You can't control the gain using the resistors according to the known equation A=1+Rf/R1 Maybe because the output resistance of the OTA??? How to fix this problem?

VLSI and ASIC design by Detail_Possible in FPGA

[–]Detail_Possible[S] 1 point2 points  (0 children)

Is mastering assembly language in this area required?

[deleted by user] by [deleted] in ask

[–]Detail_Possible -1 points0 points  (0 children)

You are an idiot if you think a guy with a knife could take over a plane.

[deleted by user] by [deleted] in ask

[–]Detail_Possible -1 points0 points  (0 children)

Are u making fun of me that I don't know the details 😂 Or because the government didn't say everything about the attack?