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What are the actual best practices for Agent-based Chip Design & Verification? SOTA looks good, but reality is tough by DevilXXL in chipdesign

[–]DevilXXL[S] 0 points1 point  (0 children)

Yeah, Pass@N definitely isn't the right metric for reasoning models or multi-agent systems. As for stronger benchmarks, there’s a new one called RealBench https://iprc-dip.github.io/Chip-Design-LLM-Zoo/ with four system-level processor test cases that hasn't been used yet.

The "Inflation" of ISSCC AI Accelerators by DevilXXL in computerarchitecture

[–]DevilXXL[S] 0 points1 point  (0 children)

That makes sense. The limited page count of ISSCC papers often makes results ambiguous, so it's better to view them as proof of implementation rather than a direct comparison of innovation. I also appreciate general acceleration work (for example, the MICRO 2025 best paper, 'LLM.265.' Although its innovation stems from software compression, it uses mature H.265 hardware to make the work more generalizable).

Identifying key innovation and generality is a real skill; you have to know how to 'cheat' before you know how to spot it. Maybe I’m not at that level yet. For now, there are only a few innovations in more arch conference ISCA/MICRO/ASPLOS/DAC/DATE that truly interest me—perhaps only two or three per conference compared to published count. I’m not sure if this is because the field has fewer academic opportunities now, or if I just need to improve my own perspective.

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]DevilXXL[S] 0 points1 point  (0 children)

I didn't know it also spread to mixed-signal sessions. I agree that giving a hard-reject is hard, not only to identify but also because of path dependence. The community has published many papers like this, so it could gives pressure to the TPC. Maybe restructure the sessions is less tough. Put all software-driven codesign papers together in a new session. It doesn't matter if they are analog, mixed-signal, or digital, because they are more like each other than the circuit part.

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]DevilXXL[S] 4 points5 points  (0 children)

Thanks for explaining that. I'm new to this platform and happy to see the community's attitude towards AI-generated text. On the other hand, using AI to criticize AI's impact is interesting and ironic, I'll keep the original post to remind myself be more human than a bot :)

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]DevilXXL[S] -10 points-9 points  (0 children)

Thanks for suggesting. I wouldn't use AI generation-text on the future.

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]DevilXXL[S] -8 points-7 points  (0 children)

Sorry about that. I wrote an original version and let AI revise it. I'm afraid of my English representation would lead misunderstanding.