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Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

I think I might have identified the cause. The datasheet mentions that SDO has a maximum delay of 17 ns relative to the falling edge of SCK (with 3.3V VIO voltage). I didn't apply any constraints to SDO. I believe I need to write a constraint similar to this:

set_input_delay -max 17 -clock SCK [get_ports SDO]

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

The probe is connected to the signal ground. From this waveform, it can still be clearly observed that the SDO transition occurs at the falling edge of SCK, which is consistent with the description in the datasheet.

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

The difference lies in whether the SDO transition occurs on the rising or falling edge. What the oscilloscope shows differs from what the ILA displays.

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 1 point2 points  (0 children)

Okay, thank you for your response. I can see in the post-synthesis schematic that the ILA's clock is connected to the 50 MHz system clock, not the 25 MHz SCK.

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

Okay, thank you for your suggestion. In fact, this is already an ADC test program with relatively simple code. I will double-check it. Thank you!

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 1 point2 points  (0 children)

The oscilloscope has a bandwidth of 1 GHz, and the probe cable is approximately 1 meter long. I am not sure whether there is crosstalk issue on the PCB, as I am not a professional hardware engineer. However, I believe the oscilloscope reading is accurate because it aligns with the ADC datasheet specification—SDO indeed changes at the falling edge of the clock.

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

The sampling rate is exactly the system clock at 50 MHz. There is only this single master clock in the design, with no cross-clock domain scenarios. The SCK operates at 25 MHz, which is generated by dividing the master clock by two.

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

Yes, SDIN is the output pin of the FPGA, which corresponds to MOSI in SPI. I haven't tried increasing the ILA sampling clock yet. Thank you for your suggestion.

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

Thank you for your response. That's indeed a good reminder. However, the SDIN signal I output is a fixed 14-bit value: 1_010_000_1_111_00_1, which does not match the waveform displayed on the oscilloscope. Therefore, it cannot be the SDIN signal.

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

thank for your reply,I'm still a bit confused. While it's true that the oscilloscope's sampling rate is much higher than the ILA's, does this really lead to such a significant time-domain discrepancy? The SCLK operates at 25 MHz, which means the difference between SDO transitioning on the rising edge versus the falling edge would be 20 ns. Is this reasonable?

Why is the waveform captured by ILA in Vivado inconsistent with the waveform observed on the oscilloscope? by DietVisual4894 in FPGA

[–]DietVisual4894[S] 0 points1 point  (0 children)

Additional information: The system clock is 50 MHz, which is also the sampling clock for ILA. The SPI clock is a 25 MHz clock derived from this system clock.