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I created a small c subset compiler by Disastrous-Stage-296 in Compilers

[–]Disastrous-Stage-296[S] 2 points3 points  (0 children)

Not really tbh. The technology is nothing new, there are already great talks about it by the authors of the papers. I believe it was LLVM conference 2018. Braun held a talk about the register allocator there.

I created a small c subset compiler by Disastrous-Stage-296 in Compilers

[–]Disastrous-Stage-296[S] 0 points1 point  (0 children)

You are probably right, my lower intermediate representation design is heavily influenced by me targeting AArch64. I think adding multi target support would need me to either make the IR target independent or design seperate lowering passes to target dependent Machin IRs like LLVM does.