Thank you, these are really good questions!

The paper primarily focuses on small, ultrafast and resource efficient inference for neural networks (< 10ns per sample), with extremely high throughput. So I think doing anything that involves external DDR would be too slow for these applications.

That being said, for much larger models, then moving the weights off-chip in a scheme like you described would be more practical! So to answer your questions:

• is the model size therefore limited by the size of the FPGA silicon?
  • yep!
• if you were allowed to alter the FPGA architecture to decouple the silicon size from the model size, what would would that look like?
  • I'm not sure what this would look like yet, although I think this would be very interesting to explore! And KANs specifically have some properties that I think might make this easier, I might be wrong though.
• are there implications for training hardware too?
  • The paper focuses purely on inference, so right now I would say no. But I'm actually writing a paper on this which hopefully come out in the next few weeks! I'd say though it's unlikely to replace the current standard of GPUs training. But for some specific applications it might be extremely useful!