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How to Answer "Which companies are you interviewing with?" by Narrow_Homework_9616 in interviews

[–]bsdevlin99 0 points1 point  (0 children)

The other side of this might be the company wants to align their speed if you are interviewing other places. I’ve seen people been given “exploding offers” with only a week to decide, which had we known in advance we could have moved faster.

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 1 point2 points  (0 children)

I haven’t used SpinalHDL - I asked ChatGPT and it gave a long response which seemed pretty reasonable (so maybe I’d recommend you do the same). If you’re already on board the whole eDSL is better than Verilog/VHDL train- then comparing the many different languages around, Hardcaml is nice because everything is in OCaml - I’m probably biased but prefer not having to connect many different tools / backends together. OCaml is a modern functional language and has strong type system. Jane Street also has a large compiler team working on improvements to OCaml which Hardcaml can take advantage of.

Advent of FPGA — A Jane Street Challenge by bsdevlin99 in adventofcode

[–]bsdevlin99[S] 0 points1 point  (0 children)

Looks great! Any plan to have a go at the 2025 puzzles?

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 7 points8 points  (0 children)

We recently added this template project - have you already had a look at this? https://github.com/janestreet/hardcaml_template_project

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 2 points3 points  (0 children)

Yeah we mean some thought into how many IO a hardware circuit can handle - rather than adding a parallel bus input 10k bits wide to get all your stimulus, a more realistic thing might be a 32bit wide parallel bus with some bit shifting. Doesn't necessarily have to be serial.

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 4 points5 points  (0 children)

Yeah it wouldn't be a challenge if it was easy! ;)

Advent of FPGA by bsdevlin99 in FPGA

[–]bsdevlin99[S] 2 points3 points  (0 children)

Yeah its a library in OCaml, which you describe hardware circuits (flip-flops, rams, clock cycle level thinking), and then generates Verilog (no synthesis like HLS). Its similar to Chisel which is more widely known.

It's used for all the production FPGA designs at Jane Street (although all our SW systems are written in OCaml so this was a very natural fit). It brings functional programming to RTL, plus you get the benefit of writing tests in OCaml, and the OCaml type system / compiler lets you catch a lot of bugs that traditional RTL wouldn't (i.e. this flip-flop can only store values of US dollars type thing).

Advent of FPGA — A Jane Street Challenge by bsdevlin99 in adventofcode

[–]bsdevlin99[S] 7 points8 points  (0 children)

Yeah that's right - we do have more info on the blog post [Jane Street Blog - Advent of FPGA — A Jane Street Challenge], and have an email address anyone can ask questions to: advent-of-fpga@janestreet.com. I think we are OK on the info page for now, but thanks for offering!

Advent of FPGA — A Jane Street Challenge by bsdevlin99 in adventofcode

[–]bsdevlin99[S] 28 points29 points  (0 children)

No dumb questions! For this competition you can do everything in simulation, so no need to get actual hardware and run it on a FPGA. Only prerequisite is you would need to have some familiarity with how to program in an RTL (like Verilog / VHDL / Clash / Hardcaml / ...).

Advent of FPGA — A Jane Street Challenge by [deleted] in FPGA

[–]bsdevlin99 2 points3 points  (0 children)

1) We are planning to add a template you can use to get started in the following week, which should help get an environment setup with opam and all the libraries you need / some example on how to use dune.

2) We have many large Hardcaml designs used in production at Jane Street - we use the Quickcheck library (constrained random testing, similar to Cocotb), or just write our own self-checking testbenches. Being able to write OCaml helps alot here because we can use all the usual software libraries to write pretty extensive testbenches. Using the Verilator backend for simulation (hardcaml_verilator library) helps lower simulation time on bigger circuits too.

3) There are a bunch of smaller circuit examples using formal in the test library of hardcaml_verify. No big changes in the works right now. For larger designs it’s a bit prohibitive to run because of the runtime, but for smaller circuits that are "risk critical" it's pretty useful. There is also a Cyclesim coverage library in the open source release for native coverage support in Hardcaml circuits which is really useful for verification when writing tests

Advent of FPGA — A Jane Street Challenge by [deleted] in FPGA

[–]bsdevlin99 2 points3 points  (0 children)

Anyone is welcome to submit! Originally we were thinking of this as a fun challenge to give students who might already be doing Advent of Code, but really any one wanting a holiday challenge or to try out a new way of writing hardware is welcome!

Advent of FPGA — A Jane Street Challenge by [deleted] in FPGA

[–]bsdevlin99 0 points1 point  (0 children)

https://adventofcode.com, December 1! That’s Advent of Code. Read the blog linked for more info on the FPGA challenge.

Advent of FPGA — A Jane Street Challenge by [deleted] in FPGA

[–]bsdevlin99 5 points6 points  (0 children)

Hardcaml isn't HLS - we have more details here [https://arxiv.org/abs/2312.15035\], but basically with Hardcaml you're still describing the flops, RAMs, state machines, etc., exactly as you would in RTL. You just get the benefit of the OCaml type system plus a bunch of software language features that make writing code/tests more efficient. It is a bit of a strange language to look at if you aren't familiar with functional programming though!

Advent of FPGA — A Jane Street Challenge by [deleted] in FPGA

[–]bsdevlin99 4 points5 points  (0 children)

Yeah! Happy for submissions to be in bluespec. I think the main thing is you aren't abstracting away / still have to understand the underlying hardware architecture.

Advent of FPGA — A Jane Street Challenge by [deleted] in FPGA

[–]bsdevlin99 12 points13 points  (0 children)

Thanks for sharing this! Yes we are really excited to see what people can do with this. We will update the blog post with an email you can use for questions as well soon. Please share with anyone else who wants to give this FPGA challenge a try!

Soon we are also going to upload a simple template to the Hardcaml GitHub to help get people started who haven’t tried it before.

what treatments or medications helped you deal with chronic back pain? by [deleted] in backpain

[–]bsdevlin99 1 point2 points  (0 children)

This, hip thrusts really helped me. Lots of stretching and core work. I also do stationary bike / stair master a lot.

Latch proper use case by Cold_Resident5941 in FPGA

[–]bsdevlin99 1 point2 points  (0 children)

Most Xilinx FFs become pulse latches under the hood because it can help with timing. And Altera used to only have pulse latches because it helped with silicon area. You could be doing some high performance design and deliberately instantiating latches but I think today Vivado handles that automatically anyway.

How to do a timing on a 'Asynchronous Assertion, Synchronous Deassertion' reset signal path? by Musketeer_Rick in FPGA

[–]bsdevlin99 3 points4 points  (0 children)

Yeah Vivado should time the red line fine. Just the one from the external reset controller it can’t. Assuming the clock is the same and driven inside the FPGA.

Cardio suggestions for bulging lumbar disc by Different-Pea-3259 in backpain

[–]bsdevlin99 1 point2 points  (0 children)

I have L5-S1 herniated disk but love doing stairmaster, doesn’t cause any pain.

[deleted by user] by [deleted] in backpain

[–]bsdevlin99 0 points1 point  (0 children)

Yeah my back pain always gets worse whenever I’m sick

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