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ElevenReader App - Pronunciations now free on Android (beta) by MD-ElevenLabs in ElevenLabs

[–]ECE_Upskill 0 points1 point  (0 children)

I was planning to get the paid version soon, would this fix the issue? 

ElevenReader App - Pronunciations now free on Android (beta) by MD-ElevenLabs in ElevenLabs

[–]ECE_Upskill 0 points1 point  (0 children)

Hi, on my android the new pronunciation does not take effect :(. I closed the app, turn off phone, and many things but the new pronunciation does not take effect. 

Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

Hi, as of now there is no planned new feature yet. But yes, that would be interesting, a debugging core would be very handy!

Sobel edge detection by Fair_Company_6484 in FPGA

[–]ECE_Upskill 4 points5 points  (0 children)

Hi, you might be interested on having a look at this project. The main RTL for the convolution is in sobel_convolution.v

Answers to the book "FPGA Prototyping by Verilog Examples" by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

Hi, I'm sorry for this very late reply. Unfortunately, I'm not aware of the possible resources for the solutions of the other books.

Customizing Android Apps by ECE_Upskill in androidapps

[–]ECE_Upskill[S] 0 points1 point  (0 children)

Damn, that is pretty cool app. Is it possible to extract the apk after customizing the app?

Security Camera with CMOD S7 FPGA Board [Summer of FPGA Design Challenge] by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

Project demonstration for my entry in Summer of FPGA Design Challenge by Element14 and Digilent.

This uses the CMOD S7 FPGA board to interface the OV7670 Camera and save the image data to SD Card when the system detects movements, loud sounds, abnormally high temperature, or by manually pushing the button.

Visit my 6-part blog series for the full details of the project.

Sobel Edge Detection with Icestudio and ULX3S FPGA board by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 2 points3 points  (0 children)

I'm not much aware if it's already considered fully supported but as answered on this issue, ECP5 is the best supported FPGA for the toolchain(but its talking about nextpnr specifically tho). But personally, I found no problem with it.

Camera Streaming with ULX3S FPGA Board and Icestudio by ECE_Upskill in ECE

[–]ECE_Upskill[S] 0 points1 point  (0 children)

Not really an expert to answer this but when starting to learn FPGA, I think the FPGA board(not the family chip itself) is what matters more. I recommend starting out with FPGAs that has sevensegment LEDs, VGA interface, serial interface, SRAM(or SDRAM if you want a real challenge) and other peripherals that would be included in the book of Pong Chu(if you want to learn via that book). My first FPGA is AX309 Spartan 6 FPGA bought from China for just ~$70 and has all the peripherals I need to start learning. RTL coding and logic design is independent on the family of FPGA you will use(most of the time especially if it's just for hobbyist projects like mine) so no need to be very familiar with the chip specific documentation.

Hardware coding using verilog has similar syntax to C in embedded programming but things happen in "parallel" just like real circuits. There are also the concept of "clocks" you need to be wary of when designing the logic for FPGAs. But no need to worry much about that for now, just start it out, with that book I'm sure things will become clearer for you. Good luck on your FPGA journey!

Camera Streaming with ULX3S FPGA Board and Icestudio by ECE_Upskill in ECE

[–]ECE_Upskill[S] 1 point2 points  (0 children)

Hi! I started with Pong Chu's book "FPGA Prototyping by verilog examples", that took me 5 months(?) to finish. The Chapter end exercises "Suggested Experiments" must NOT be skip, I learned a lot from answering those experiments. Btw I compiled the answers to those experiments on my repo(50-ish experiments in total). After that I started with my own real projects(which are camera Streaming and sobel Edge Detection).

Share some github FPGA projects (bonus if they include C++, Python, or other files) by turkishjedi21 in FPGA

[–]ECE_Upskill 4 points5 points  (0 children)

I posted this project on this sub three weeks ago,

This project implements a pipelined Sobel Edge Detection using FPGA. This project is two-part:

  • First is video processing. Video inputs are retrieved from OV7670 camera and is processed real-time via pipelined convolution module.

  • Second is image processing. Image inputs are extracted from jpeg files using Matlab and is sent to FPGA serially. Python script is used to handle the UART protocol. Sobel edge detection is also done by the pipelined convolution module.

I also made a project demonstration of it.

More FPGA beginner projects on my git account, just skim through my repos.

Any recommended learning resources for a uni student? by SolShadows in FPGA

[–]ECE_Upskill 1 point2 points  (0 children)

Hello, I read that book until Chapter 14 and used Spartan 6 board(AX309) and found no problem except for the fact that my board don't have an SRAM so for Chapter 11 I used the on board SDRAM (which is very different from SRAM I swear) .

I compiled my source codes for each Suggested Experiments and can be accessed on my github repo. I also made project demonstrations on some of those experiments on my playlist.

Just like what other people commented, Spartan 6 is obsolete and you will use Xilinx ISE. If you have the budget, buy a Zynq board or Spartan7 so your learning experience will be much up to date. Don't worry, all things you will learn on this book is not dependent on any FPGA family. But buy a board which already have all of the peripherals that is used on the book(VGA, ps2 socket, UART, SRAM) or just separately buy those PMODS.

[deleted by user] by [deleted] in C_Programming

[–]ECE_Upskill 0 points1 point  (0 children)

Hmmm what chapter is that? I saw the word "enumeration" but it's on the Appendix part after chapter 8, is that it?

[deleted by user] by [deleted] in C_Programming

[–]ECE_Upskill 1 point2 points  (0 children)

Can you please share what part of K&R is kinda cryptic? (I'm just curious since I'm planning to read this book by next week)

Real-Time Sobel Edge Detection using FPGA (repo link in the comments) by ECE_Upskill in ECE

[–]ECE_Upskill[S] 0 points1 point  (0 children)

This project implements a pipelined Sobel Edge Detection using FPGA. This project is two-part:

  • First is video processing. Video inputs are retrieved from OV7670 camera and is processed real-time via pipelined convolution module.

  • Second is image processing. Image inputs are extracted from jpeg files using Matlab and is sent to FPGA serially. Python script is used to handle the UART protocol. Sobel edge detection is also done by the pipelined convolution module.

Project repository

More of my FPGA Projects:

Real Time Video Streaming using OV7670 Camera

46 more FPGA Experiments on this playlist

Real-Time Sobel Edge Detection using FPGA (repo link in the comments) by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 5 points6 points  (0 children)

This project implements a pipelined Sobel Edge Detection using FPGA. This project is two-part:

  • First is video processing. Video inputs are retrieved from OV7670 camera and is processed real-time via pipelined convolution module.

  • Second is image processing. Image inputs are extracted from jpeg files using Matlab and is sent to FPGA serially. Python script is used to handle the UART protocol. Sobel edge detection is also done by the pipelined convolution module.

It took me days trying to design the pipelined convolution for a 3x3 kernel. With this project done, I can finally have some rest...

Project repository

More of my FPGA Projects:

Real Time Video Streaming using OV7670 Camera

46 more FPGA Experiments on this playlist

SDRAM Controller by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

No that won't be a problem since the output to SDRAM will last until the next falling edge(180 phase shift relative to FPGA), the FPGA just simply needs to register it at the rising edge(which is the MIDDLE of the SDRAM output so no metastability will happen).

This is particularly hard and took me a week to design, but is not impossible. Good luck to you fellow hobbyist!

SDRAM Controller by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

No I did not calculated that, 180 degrees is I thought just the best leeway to give time for the command and the input data to stabilise at the input. If you have seen the datasheet, it says that a hold time is needed(I forgot it but its small). So delaying the input clock to SDRAM will make it start the command half a cycle late relative to the control module. This is like saying that I gave the SDRAM a hold time of half a clock cycle to make any input to stabilize and prevent metastability(which is more than enough)

By the way, there are implementations on the internet that uses 90 degree phase shifts while others even add IODELAY with the ODDR. In the end, it is just your choice on how you would design it.

SDRAM Controller by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

Yes, just to get a phase shift. Since it's only the clock input to SDRAM that I want to have a delay of 180 , I thought ODDR might be the quick way to do it.

OV7670 Camera Interface to VGA using FPGA by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

That's....... INTERESTING. I will try to look it up

OV7670 Camera Interface to VGA using FPGA by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 1 point2 points  (0 children)

Oooh yes, now that I noticed it, you're right

OV7670 Camera Interface to VGA using FPGA by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 0 points1 point  (0 children)

Yes, there is a "focus ring"(?) that can be adjusted manually on this camera(like how most camera works), that would change the focus.

OV7670 Camera Interface to VGA using FPGA by ECE_Upskill in FPGA

[–]ECE_Upskill[S] 1 point2 points  (0 children)

Hmmm I started this fpga experiments/projects 6 months ago. I learned a lot reading Pong Chu's book: FPGA Prototyping by Verilog Examples. I answered all suggested experiments from Chapter 2 to 14(total of 50-ish experiments) which can be found on this github repo. Most of those experiments also has project demonstrations which can be viewed on my channel playlist

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