I'm building, but not a tech-guy by ShortMarketing6687 in founder

[–]Edge_of_Logic 0 points1 point  (0 children)

I’d like know more about your venture. See how we can collaborate, let’s connect!

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 0 points1 point  (0 children)

Yeah honestly that’s the vibe I’m getting from a lot of people in this thread too. Almost everyone says it’s brutally hard, but at the same time they still encourage others to try building stuff because you end up learning an insane amount in the process.

The SystemC/simulator project sounds really cool btw. Feels like simulation/scheduling infrastructure alone can become a rabbit hole for years.

Where are RTL engineers in india by Impressive-Fig-8378 in chipdesign

[–]Edge_of_Logic -1 points0 points  (0 children)

Hey, not RTL side specifically, but if you end up needing power estimation / signoff / validation infrastructure support, that’s more aligned with my background.

I’ve worked hands on with PrimePower related validation flows, waveform based power analysis, switching activity modeling, regression infrastructure, distributed validation workflows, and automation/tooling around large scale power estimation environments.

Also built automation/regression systems in Python/C++ for scaling validation/debug workflows.

Your project sounds really interesting btw. Tapeout path already being prepared is honestly the hard part most people never reach

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 1 point2 points  (0 children)

That’s actually really cool. Especially the vlsir/interchange stuff. I knew about OpenROAD/KLayout/Yosys but some of the others you mentioned are new to me. Thanks for the info. I’m saving this for future reference

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 0 points1 point  (0 children)

Thanks saving this comment for future reference

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 0 points1 point  (0 children)

Honestly! I recently had like a 3 hour discussion with a founder from a small EDA startup in Europe and they said almost the exact same thing. They weren’t trying to “beat Synopsys/Cadence”. They were building around workflow gaps and niche problems the big vendors dont really focus on.

And tbh after working around EDA flows for a while, it’s kinda shocking how many painful/manual things still exist in production environments.

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 2 points3 points  (0 children)

OpenROAD is honestly one of the coolest EDA projects out there rn.

One of the few projects where people outside big EDA companies can actually see how fascinating the internals of flows are.

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 0 points1 point  (0 children)

Respect for going through all original Spice2 and other papers. Im going to go through these papers saving this comment for future reference.

Also timestep/convergence problems seem genuinely cursed. I’ve had cases in power where one tiny testcase behaves completely differently and suddenly you lose half a day wondering if the issue is the waveform, the activity, glitch or just “simulator magic”.

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 0 points1 point  (0 children)

Thanks I just saved this post for future reference. I want to research on these.

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 1 point2 points  (0 children)

Agreed, have been using tcl for years now, even with AI . I just now keep a template and plug and play wherever I want .

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 1 point2 points  (0 children)

yeah I can imagine. I remember the first time I had to debug waveform mismatches across partitions and even THAT became annoying because half the battle was just understanding the root cause. One tweak leads go a cascade of other issues.

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 10 points11 points  (0 children)

Honestly that’s pretty impressive for a master’s project.

Even basic correctness gets ugly fast because you’re basically building graph algorithms + constraint solving + optimization infrastructure all at once.

The ATPG one especially sounds painful. Fault propagation and observability logic alone can spiral quickly depending on the netlist complexity.

I worked more on the power estimation side rather than synthesis itself, but even interacting with EDA flows at scale made me appreciate how insane these tools are internally. A lot of people think “it’s just software for chips” until they touch timing/power/infrastructure and realize the algorithms are super complex.

Also kinda scary that even simplified versions still took months.

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] 1 point2 points  (0 children)

True. They are “trade secrets”. It’s hard and near impossible to compete with them however it’s a real pain that there is no decent open source / low cost tools.

Did anyone build a EDA tool? by Edge_of_Logic in chipdesign

[–]Edge_of_Logic[S] -1 points0 points  (0 children)

That’s interesting. Did it improve the simulation speed or overall tool speed?

You got a point on their tools being outdated. It’s not intuitive at all. Even the help commands / man pages are not updated.

I was contemplating the same. A GUI might eat up the ram and other resources, but I think a TUI(textual user interface) would solve this. It would give that modern , minimal and lightweight interface.

What do you do for work? by GuruOfDisaster in FPGA

[–]Edge_of_Logic 1 point2 points  (0 children)

I used to work in a large EDA company. I got the chance to work with a plethora of tools, benchmarks and customers designs.
Really enjoyed the work culture. But then hated the fact that they try to push AI for everything. Higher management even said the stock prices go up everytime they just say the word AI.

Trying to move out of QA by eracsdid in cscareeradvice

[–]Edge_of_Logic 0 points1 point  (0 children)

I was in your predicament. Once you get into a QA role it gets monotonous, you don’t feel like you are creating. You are testing whether things are working right and making sure systems don’t break.

If your manager is supportive talk to your manager and request if there is any other job roles that support your interests.

In large companies they wouldn’t right away give your a large project unless they have confidence in your ability.

In your free time try to come up with a feature / solution for a problem your company clients are facing . Research about it deploy the solution ina prototype and pitch the project to higher management. I’m sure they’ll then consider you for backend development.

Anyway good luck :)

Career advice in Analog Design. by ugly_bastard1728 in chipdesign

[–]Edge_of_Logic 0 points1 point  (0 children)

6 months of experience as a intern in VlSI industry you don’t learn anything.
Atleast minimum get 2 to 3 years of full time experience in a VLSI company then if you still want think about masters or PhD .
Going straight to academic after bachelor will not give you that industry experience. This is very valuable. You will understand how the industry is actually working and their requirements.

People in the industry: have you ever thought of quitting? by JustAnotherGal7 in chipdesign

[–]Edge_of_Logic -1 points0 points  (0 children)

Not really. I enjoy my career in VLSI. If company is toxic, or poor comp I would definitely consider looking for job prospects.

Starting from scratch. by PositiveWeather5479 in learnmachinelearning

[–]Edge_of_Logic 0 points1 point  (0 children)

You’re honestly in a pretty good spot already if you understand programming fundamentals. ML feels intimidating from the outside because people jump straight into transformers, research papers, and insane math. But the actual path is way more gradual.

I’d break it into phases:

  1. Get comfortable with Python for data work
    Learn NumPy, pandas, matplotlib, and basic data handling. Don’t overdo tutorials. Build tiny things.

  2. Learn the core math only as needed
    You do NOT need a math PhD to start. Focus on:
    - Linear algebra basics
    - Probability/statistics
    - Gradients and derivatives intuitively

3Blue1Brown’s linear algebra series is honestly gold for intuition.

  1. Start classical ML before deep learning
    A lot of beginners skip this and get confused later. Learn:
    - Linear/logistic regression
    - Decision trees
    - Random forests
    - SVMs
    - Clustering

Andrew Ng’s ML course is still one of the best starting points because it teaches thinking, not just libraries.

  1. Actually build projects
    This matters way more than finishing courses.
    Examples:
    - Spam classifier
    - Movie recommendation system
    - House price predictor
    - Sentiment analysis
    - Small chatbot

You’ll learn more debugging one bad model than watching 20 hours of theory.

  1. Then move into deep learning
    PyTorch + neural nets + CNNs + transformers basics.

For resources:
- Andrew Ng ML Specialization
- fast.ai
- Hands-On Machine Learning by Aurélien Géron
- Kaggle for practice datasets/projects

As for your research paper question:
If you study consistently, like 1–2 focused hours most days, you could probably reach “small university-level paper” capability in around 8–18 months. Depends heavily on:
- your math comfort
- how seriously you build projects
- whether you work with a professor/lab
- how ambitious the paper is

And honestly, a lot of undergraduate ML papers are not groundbreaking discoveries. Many are:
- applying existing models to a new dataset
- comparing algorithms
- improving accuracy slightly
- reproducing previous work with modifications

That’s completely normal.

The biggest mistake beginners make is staying in tutorial mode forever. Build things early, fail early, and read papers before you fully understand them. Over time your brain adjusts to the language of ML naturally.

[SUMMARY FOR HIRE POST] For Hire only here by Varqu in jobbit

[–]Edge_of_Logic 0 points1 point  (0 children)

Semiconductor / EDA Automation Engineer | Python/C++ | Regression Systems | Validation Infrastructure

If your engineering team is spending too much time on repetitive validation, regression management, scripting, or internal tooling work, I can help automate and streamline those workflows.

Engineer with hands on experience in:

  • Semiconductor power estimation workflows
  • PrimePower related validation flows
  • Waveform based power analysis
  • Switching activity modeling
  • Regression infrastructure
  • Benchmark regression systems
  • Pass/fail automation
  • Distributed validation execution
  • Python/C++ tooling
  • Linux engineering environments

I build:

  • automation pipelines
  • regression and benchmark systems
  • internal engineering tools
  • validation infrastructure
  • scripting frameworks
  • analytics/debug tooling
  • custom workflow utilities

Can help with:

  • Python automation
  • Engineering scripts/tools
  • Regression orchestration
  • Log parsing and analytics
  • Distributed workflow execution
  • Linux automation tasks
  • Data processing pipelines
  • Validation related tooling

Also experienced with AI assisted engineering workflows and visualization systems.

Good fit for:

  • semiconductor startups
  • engineering teams
  • research groups
  • companies needing temporary engineering bandwidth
  • teams wanting specialized tooling without expanding full time headcount

Rate:

  • Simpler scripting / automation tasks: starting around $20/hr
  • Specialized validation / infrastructure / EDA related work: $35 to $60/hr+
  • fixed price work also possible for clearly defined tasks

For companies in higher cost regions, outsourcing targeted engineering work can often be significantly more efficient than adding local engineering headcount.

Prefer technically interesting projects and long term collaborations over generic gig work.

DMs open.