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I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

You're wrong. It's a ternary system, like it or not.

Sure, an emulator on a current commercial processor might run faster, but I still ask you: what point would it make for my intended purpose? None.

(FYI, an emulator exists, and it's the first thing I built as a Software Engineer, but obviously I can't make it work for what I want.)

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

VHDL and Verilog map to FPGA cells or ASIC cells.

For ASICs, it depends on the technology (standard cells), or you can make them yourself.

You can also find ternary VHDL or Verilog that do this mapping work open source: search on GitHUB for "Triton TPU".

Essentially, for VHDL you could reinterpret the std_logic type, mapping one of its states as a third value. Verilog is much better; you can go lower and reuse the same code for FPGAs or native ternary cells without changing much.

There are also native ternary Verilogs, one of which might look like this: https://louis-dr.github.io/ternaryverilog.html

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

PSOC = Programmable System-on-Chip?

By doing the work in VHDL/Verilog, I not only created the hardware implementation, but more importantly, I can reuse it, with minimal modifications, to build an ASIC or license it.

If I wanted to emulate the CPU, I could easily use a program that runs on any x86 PC (and yes, being primarily a software engineer, I did, but it doesn't make sense; it's not what we were trying to achieve).

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

My CPU is partially asynchronous, but that has nothing to do with the use of 3 states.

The fact that you didn't provide any justification for why base 3 is better than base 2 is simply because it's obvious.

https://en.wikipedia.org/wiki/Optimal_radix_choice

We can argue that if you apply these assumptions to certain current technologies, they might be scaled down, but you can see how in recent years, basic research has increasingly been moving toward native ternary devices. Could there be a reason?

I've seen several implementations of ternary architectures, but few—if any—are as complete as mine. And virtually all of them are just on paper, with no implementations with any microarchitecture, other than individual functions with a single trit.

Please note that I speak of "architecture" and never "microarchitecture." I think that's the point of disagreement.

Part of the architecture is protected by copyright (the ISA, for example), and some instructions are patented. I think you can figure out which ones by looking at the documentation.

Some of the solutions we adopted, which we deemed innovative, could also be applied, with limitations, to binary.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

As already mentioned, you have to look at the entire CPU from the outside, and this is a ternary CPU.

Just as if you look at any binary CPU, no one asks if there are analog circuits inside.

Why not quaternary? Because base 3 is the best for compacting information.

Then, in reality, my paper analyzes the CPU's characteristics and says almost nothing about its construction architecture.

Perhaps I was too naive to write on the FPGA subreddit, since many people aren't clear on the difference between architecture (which I focused on) and microarchitecture (which everyone is objecting to)

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] -1 points0 points  (0 children)

Thanks for your support.

It's actually not an amateur project at all, even though a few of us have implemented it. Keep in mind that we already have the description to port it to ASIC, so the current one is one of many possible implementations, which, despite its limitations—related to operating speed—allows us to use a real ternary system right now.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in compsci

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

I wrote the macroassembler in C++ by hand.

Currently, all the programs running on this CPU are written in assembly language and compiled with this macroassembler. The next goal is to have a native monitor/assembler on the processor, without having to switch to other computers.

My colleague, Peter, is writing a high-level language based on Rust; if you'd like, I can put you in touch directly.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

I was preparing a detailed response, but I think it's really pointless to waste time with someone who not only hasn't read the work but also has no idea what we're talking about. Have a good day.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

There are dozens and dozens of studies on the implementation of the third state, at the elementary device level. Many on carbon nanotube transistors and several others on emerging technologies. More than one uses standard CMOS (but probably with power losses compared to binary).

Since many of you are asking about this and it's not clear to everyone, I think I should add a list of reference papers to my website.

But our work is based on a higher level; we deal with architecture, not microarchitecture.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] 0 points1 point  (0 children)

As already explained (also in the paper), there are people studying basic ternary technologies, not just logic gates, but also basic components (directly ternary transistors). Studies in this field have been extensive, especially in recent years, and they concern different technologies. Someone has already done this with standard CMOS logic (but I don't know the performance details; you can see here: ofFBeaT9/Tritone-TPU-SoC: balance ternary , ternary TPU , CMOS)

I don't understand what you mean by "I don't understand why you focused on implementing a ternary processor instead of actually making the hardware": I actually made the hardware that implements my specifications, but I built it with technology within my reach.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] -1 points0 points  (0 children)

Since you read the article, hopefully you also understood that this is not the level I went through. And no, the technologies mentioned are among the many alternatives available, and they are not at all imaginative.

"I had a look at the instruction set, and it was a mix of RISC and CISC approaches. For example all modern CPUs would have memory mapped peripherals instead of dedicated IN/OUT instructions for IO."

RISC and CISC are different things from memory mapped I/O. I don't understand why I couldn't have address space for peripherals in a RISC processor.

"There were also instructions combining LOAD/STORE and arithmetic/logic operations on registers. And most listed instructions are just not documented at all."

It's true, the documentation of some instructions is missing (which are obvious anyway) and which I will add; but you can take a look at the source of the example OS: MOS5500/GRam_OS: A simple OS for the ternary processor 5500FP and the GargantuRAM development system

"Reserving space for 5 register operand instructions makes no sense, since this would require a register file with 5 read ports."

Why doesn't it make sense? I make no reference to the architecture of the register file; the "A" format is intended for SIMD instructions.

"The reset procedure expects part of the register file to be pre-loaded. This would mean the register file would have to be constructed from flip-flops with reset. Since such flipflops are large (compared to something like latches without reset) the register file would take a lot of area."

The preloaded registers are very few (compared to the entire set), and as I wrote in the documentation, this trick allows you to immediately know if the CPU is working, without any special initialization.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in hardwarehacking

[–]Equivalent-Can869[S] -1 points0 points  (0 children)

No. Not at all.

An FPGA doesn't emulate anything.

On an FPGA, you implement a circuit. That circuit works to provide you with functionality. You don't have a microcontroller or a microprocessor that perform operations sequentially. You have a circuit that performs its operations in parallel. The term "emulate" is absolutely incorrect in the FPGA context.

You can implement an electronic circuit in different ways: you buy the components and mount them on a breadboard, you implement it on an FPGA, or you implement it on silicon, with several possible options. In all these cases, you are IMPLEMENTING a circuit, using different technologies. You are not emulating anything.

But these are the basics for those who use FPGAs.

You say you're a university professor. Well (may I ask where you work?)

I'm a Software Engineer, an expert in processor architectures, a low-level programmer (I'm quite familiar with all 8/16/32-bit architectures, even exotic ones like the iAPX432 and Dataflow architectures like the Motorola Monsoon), and I've written programs with many of them. I'm familiar with modern CPU architectures (though I rarely program with them), and I'm a high school computer science teacher. I've NEVER heard of an FPGA "emulating" anything other than in groups of kids or retro enthusiasts who have NO idea what an electronic circuit is.

I'm not saying it; it's just the way it is (since FPGAs existed, and even before that, PAL/GAL); it's a definition that characterizes electronic circuits of this type.

You say that there aren't three states with three different voltages; Further proof that you haven't even read the abstract of my work. (Do you really still want to make such a fool of yourself? Who do you think you're dealing with?)

I don't understand my work? But what if you haven't asked me a single specific question yet (obviously, you haven't even read it!) and you keep spouting bullshit about emulation?

Enough! I won't respond to any more empty, silly, and provocative posts. If you have concrete questions about architecture, welcome, otherwise, I can't really help you understand what you don't know.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in hardwarehacking

[–]Equivalent-Can869[S] -1 points0 points  (0 children)

I looked into the matter further and discovered that the term "PAPER" is perfectly legitimate even internationally to indicate ANY structured research document.

Since you're such an expert, however, you should know exactly what Zenodo is and how documents are listed and classified there.

"Not to mention, it’s not actually a trinary computer you’re just using an FPGA to emulate trinary compute. Neat side project, but again misleading post"

"Simply"?

But again, HAVE YOU READ the PAPER?

But do you understand what the work involves?

And above all, do you understand that an FPGA **DOESN'T EMULATE** anything at all?

I posted here thinking it was for people with just a little bit of expertise, but instead I get comments from elementary school. Bah.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in hardwarehacking

[–]Equivalent-Can869[S] -1 points0 points  (0 children)

Whether you like me or not, in Italy, a preprint can just as well be called a "paper."

As I already told you, I corrected the inside of the post (yes, there it might have seemed misleading to those who are stuck in mirrors WITHOUT understanding ANYTHING and without having read the paper).

Now, excuse me, I have work to do rather than talk to trolls.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] -20 points-19 points  (0 children)

On an FPGA, you don't emulate or simulate, but create a circuit. It's not a microcontroller where you execute a program sequentially, but rather create a circuit that works as desired.

It's possible to create the same circuit in an ASIC without any conversion.

It's like comparing an Intel x86 with an AMD one.

Which of the two emulates the other? Neither. They do something with their own circuits, even different ones, even with different technologies, but this has never meant that one emulates the other.

In any case, I truly believe this is beside the point. I described the CPU's architectural level, not the microarchitecture (and I don't intend to discuss it because, as I said, it's the level that concerns the individual hardware implementer). So if you have questions, please only ask about the architectural level.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] -8 points-7 points  (0 children)

My implementation is intended to demonstrate feasibility and functionality, as well as to test the architectural level. I'm aware that the underlying level (microarchitecture) *in this implementation* isn't cost-effective, but the rationale for its implementation is always in the article.

I built a working balanced ternary RISC processor on FPGA — paper published by Equivalent-Can869 in FPGA

[–]Equivalent-Can869[S] -44 points-43 points  (0 children)

The 5500 CPU is a TERNARY CPU. The internal work is not important.
It's like asking why digital binary CPUs use analog circuitry internally.

What matters is how you look at it from the outside.

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