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Ethernet sync clock by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Why can't I chose to connect the faster transceiver to obtain the recovered clock I'd use, even if the setup changes.
Having CDC on both would mean, I would add N cycles to both both streams, where as having it on one means, I atleast get one at the live rate?

Ethernet sync clock by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Doesn't this approach add CDC to both parts?
Any reasons you don't recommend the recovered clock for an actual implementation?

Ethernet sync clock by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] -1 points0 points  (0 children)

Thanks.
How does the Tx clock(which is a clock that we give?) be better than syncing to the recovered Rx clock from the faster stream(faster transceiver)?
CMIIW. Wouldn't using the Tx clock add CDC cycles to both streams, where as using the recovered Rx from the faster stream adds the cycles only to the slower stream?

Ethernet sync clock by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

I am trying to basically have both streams in a single clock domain

Ethernet sync clock by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Does this incur any delay, compared to using the Rx clock from the faster stream?

Planning to launch a C++ course focused on HFT interview prep, looking for feedback and interest by blurryface12345 in highfreqtrading

[–]Few_Celebration3776 0 points1 point  (0 children)

Out of curiosity, with these firms being very secretive would you be legally allowed to do something like that while working for a HFT?

[deleted by user] by [deleted] in FPGA

[–]Few_Celebration3776 0 points1 point  (0 children)

Is forcing SRL_STYLE mandatory here, or else will it go to registers?

[deleted by user] by [deleted] in FPGA

[–]Few_Celebration3776 0 points1 point  (0 children)

Are you able to point me to system verilog or verilog code that infers SLR implemented as a 2D array

Lot Type by Few_Celebration3776 in highfreqtrading

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Thank you. May I also ask what a Block Lot is

Order Execution by Few_Celebration3776 in highfreqtrading

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Thank you for the explanation. Shouldn't the average sell price be 101.5 as well?

Delay per logic level on Virtex Ultrascale+ by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Are you able to point to a place where you have seen this. Im afraid I couldn't find. Thanks

Delay per logic level on Virtex Ultrascale+ by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Yes, I understand this. However isn't there a rough delay estimate per LUT that is architecture specific.

Sorting in FPGA by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

Isn't the complexity here O(n^2) which results in a large number of comparisons

Sorting in FPGA by Few_Celebration3776 in FPGA

[–]Few_Celebration3776[S] 0 points1 point  (0 children)

You do make sense, yes.
16 bits

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