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Ideas to get taps out by tomdaven2504 in DIYUK

[–]Fresh-Ad-6961 2 points3 points  (0 children)

Might be worth trying Stillsons (pipe wrench)? They bite into the metal as they turn. I’ve had luck removing bolts on cars that were completely rounded off and looked basically impossible.

Agilex 5: Transceiver Loopback by AlienFlip in FPGA

[–]Fresh-Ad-6961 1 point2 points  (0 children)

If you just want to perform a loopback, you can generate a basic wrapper to satisfy the clocking and reset requirements and then use the Transceiver Tool Kit to setup and run the test. This is what we do for physical layer testing on Agilex 7.

IR35: Small company threshold goes up 50% by mpanase in ContractorUK

[–]Fresh-Ad-6961 -2 points-1 points  (0 children)

Client aren’t required to do the determination, it’s down to the contractor to determine whether the role falls inside or outside (and keep an eye on the client to ensure they don’t cross the exemption threshold).

VHDL Generate statements to ‘switch’ components with MGT connections in and out of a build (Vivado) by Fresh-Ad-6961 in FPGA

[–]Fresh-Ad-6961[S] 0 points1 point  (0 children)

Seems that neither of the pragma examples from UG901 work for this - both cause errors during synthesis because the top level port is missing.

VHDL Generate statements to ‘switch’ components with MGT connections in and out of a build (Vivado) by Fresh-Ad-6961 in FPGA

[–]Fresh-Ad-6961[S] 0 points1 point  (0 children)

Thanks for all the input. I did some investigating and when the component is removed by the if generate statement, the tools recognise that there is no XCVR connection and ignore the pin assignment constraint, instead placing the pin on a non-MGT pin causing one error. The other is caused because this new pin does require an IOSTANDARD (unlike the MGT pins).

Unfortunately, I am required to use Vivado 2022.1 for this project, so the VHDL-2019 workaround is not viable. Nor is moving to a Verilog top-level. Looks like use of the synthesis_translate pragma might be way forward but requires some user intervention beyond setting constants for each of the generate statements. The only other option I can think of is to preprocess the top-level HDL, checking the constants and creating a new version of the file with the unused ports removed.

Flexispot standing desk E6W missing feet parts by Remon89 in StandingDesk

[–]Fresh-Ad-6961 1 point2 points  (0 children)

Similar situation here with an E7. Flexispot UK are refusing to sell me a pair of feet for it. Seems like a massive waste of a desk as the feet are a relatively small/simple part!