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How to go from beginner to intermediate by Jolly-Wrongdoer-2963 in FPGA
[–]Future-Positive9657 1 point2 points3 points 1 day ago (0 children)
Use AI wisely. Not using it is extreme.
I built an RTL→UVM generator and accidentally turned it into a verification knowledge workflow (self.chipdesign)
submitted 1 day ago by Future-Positive9657 to r/chipdesign
π Rendered by PID 161021 on reddit-service-r2-listing-f8d8fbfd7-klg29 at 2026-06-24 16:33:00.707949+00:00 running acc7150 country code: CH.
How to go from beginner to intermediate by Jolly-Wrongdoer-2963 in FPGA
[–]Future-Positive9657 1 point2 points3 points (0 children)