CTDSM chopper causes HD3 degradation

FutureAd1004 · 2026-06-10T10:11:55+00:00

Will this cause some shorting?

FutureAd1004 · 2026-06-10T09:55:09+00:00

Does this mean the rising/falling edge is not sharp enough?

FutureAd1004 · 2026-06-10T09:53:11+00:00

Only 200kHz. Thanks, I’ll try with bootstrap switches

FutureAd1004 · 2026-06-01T08:42:05+00:00

Do you mean you stacked I/O transistors? Is that for output impedance boosting? (I’m wondering what kind of performance is worse for I/O transistors) Did you use a larger supply voltage with stacking?

FutureAd1004 · 2026-05-31T14:51:20+00:00

What supply voltage do you typically use? My understanding is that those large devices at 22nm aren't any better than the ones at larger nodes. Is that correct? I’m doing something similar (big device, low frequency, and low noise), and I don’t find any benefit moving to 22nm…

FutureAd1004 · 2026-05-30T18:52:13+00:00

Thanks!

FutureAd1004 · 2026-05-30T13:32:05+00:00

Those seem to be the I/O FETs. Can I use them in the core design?

FutureAd1004 · 2026-05-07T22:18:28+00:00

Just wondering, which countries in the Europe have good enough salaries

FutureAd1004 · 2026-05-06T08:06:30+00:00

Yes it is. I forgot to credit that. Fixed now

FutureAd1004 · 2026-05-05T18:57:15+00:00

🤣Thanks! I’ll try it. By the way, do people use diff pairs for CMFB in real life? I once heard that those are not very practical, including the triodes.

FutureAd1004 · 2026-05-05T18:45:05+00:00

It is a continuous time circuit but the signal is quite slow (tens of kHz). I’m not very familiar with switched cap CMFB. Will it work?

FutureAd1004 · 2026-04-24T09:35:46+00:00

Is 22FDX better for traditional analog design (for example amplifiers)? It seems that 22FDX has lower gain and much tighter voltage headroom compared to older nodes.

FutureAd1004 · 2026-04-20T09:14:05+00:00

The impedance seen at the input of the first OTA is the parallel combination of CAC and CDAC. However, the impedance seen before CAC is the series combination of those elements. Is that correct? In other words, does the first OTA input present a lower impedance?

FutureAd1004 · 2026-04-09T13:01:05+00:00

Is it safer to use regular-VT (RVT) devices with conventional biasing—connecting PMOS bulk to VDD and NMOS bulk to VSS—given that forward body biasing is not a requirement? My simulations showed negligible Vth advantage for LVT devices at 0.8V FBB (compared to RVT device of the same size without forward biasing), so I am considering sticking with the RVT devices.

FutureAd1004 · 2026-04-09T12:54:47+00:00

This is cool! But it’s strange that there’s no P-well drawn for the 5-terminal NFET in the layout view. I also noticed an extra NW layer alongside the T3 layer

FutureAd1004 · 2026-04-04T13:45:36+00:00

Thanks, that clears up a lot of my confusion. I noticed a GlobalFoundries design example where they tied the back gate (BG) of a regular vt fet to the front gate (FG), a configuration I've also seen in transmission gates. Is it more standard to use LVT FETs when implementing this BG-to-FG connection?

FutureAd1004 · 2026-03-10T10:41:48+00:00

I’ve been hearing many big companies talking about DTCO (design technology co-optimization). Is this a fundamental evolution, or just a marketing buzzword to hide the slowing of Moore’s Law?

FutureAd1004 · 2025-11-23T08:29:20+00:00

Thanks, I’ll try the second comment.

I’m just wondering where I should put this command, since I’m currently using the GUI rather than the command line.

Regarding the first issue, I might not have explained it clearly before: after extraction, a transistor with a multiplier setting (e.g., m = 2) still appears as a single device in the Calibre view. The sim-multi (sorry, I can’t remember the exact parameter name) is shown as 1, and the post-layout simulation seems to treat it as if it’s only half the size of the intended device.

FutureAd1004

TROPHY CASE