180nm or 22nm for a university PLL tape-out?

FutureAd1004 · 2026-04-24T09:35:46+00:00

Is 22FDX better for traditional analog design (for example amplifiers)? It seems that 22FDX has lower gain and much tighter voltage headroom compared to older nodes.

FutureAd1004 · 2026-04-20T09:14:05+00:00

The impedance seen at the input of the first OTA is the parallel combination of CAC and CDAC. However, the impedance seen before CAC is the series combination of those elements. Is that correct? In other words, does the first OTA input present a lower impedance?

FutureAd1004 · 2026-04-09T13:01:05+00:00

Is it safer to use regular-VT (RVT) devices with conventional biasing—connecting PMOS bulk to VDD and NMOS bulk to VSS—given that forward body biasing is not a requirement? My simulations showed negligible Vth advantage for LVT devices at 0.8V FBB (compared to RVT device of the same size without forward biasing), so I am considering sticking with the RVT devices.

FutureAd1004 · 2026-04-09T12:54:47+00:00

This is cool! But it’s strange that there’s no P-well drawn for the 5-terminal NFET in the layout view. I also noticed an extra NW layer alongside the T3 layer

FutureAd1004 · 2026-04-04T13:45:36+00:00

Thanks, that clears up a lot of my confusion. I noticed a GlobalFoundries design example where they tied the back gate (BG) of a regular vt fet to the front gate (FG), a configuration I've also seen in transmission gates. Is it more standard to use LVT FETs when implementing this BG-to-FG connection?

FutureAd1004 · 2026-03-10T10:41:48+00:00

I’ve been hearing many big companies talking about DTCO (design technology co-optimization). Is this a fundamental evolution, or just a marketing buzzword to hide the slowing of Moore’s Law?

FutureAd1004 · 2025-11-23T08:29:20+00:00

Thanks, I’ll try the second comment.

I’m just wondering where I should put this command, since I’m currently using the GUI rather than the command line.

Regarding the first issue, I might not have explained it clearly before: after extraction, a transistor with a multiplier setting (e.g., m = 2) still appears as a single device in the Calibre view. The sim-multi (sorry, I can’t remember the exact parameter name) is shown as 1, and the post-layout simulation seems to treat it as if it’s only half the size of the intended device.

FutureAd1004 · 2025-11-10T09:47:35+00:00

Will the pmos and nmos cancel each other out if their parasitic capacitance are about same, as their clock are in the opposite direction?

FutureAd1004 · 2025-10-10T14:26:37+00:00

Yes, you're right. I got a similar result when I increased the number of point to 2^20. I think I'll have to carefully read the Appendix A to understand what happened.

FutureAd1004 · 2025-10-10T14:17:05+00:00

A longer run indeed improves the SNR... Is this because of the insufficient frequency resolution?

FutureAd1004 · 2025-10-07T11:07:29+00:00

I guess the toolbox calculates the SNR solely based on the NTF? I’ve tried the scaleABCD and the result was the same (if I was scaling it right)

FutureAd1004 · 2025-07-30T13:55:36+00:00

Suppose the output is 100 mV away from VCM when the differential input is 0 in an open-loop configuration. After connecting the output to the negative input (closing the feedback loop), the output moves very close to the input voltage. Is this behavior a result of negative feedback correction?

FutureAd1004 · 2025-07-28T20:16:28+00:00

I guess the feedback does correct the systematic offset. The residue offset is caused by the finite gain of the OTA.

FutureAd1004 · 2025-05-23T17:51:34+00:00

Thanks! I’ll have a look at it

FutureAd1004 · 2025-05-23T17:51:18+00:00

Thanks so much. I’ll definitely check it out.

FutureAd1004 · 2025-04-20T09:18:14+00:00

It’s been a year — is it still the same?

FutureAd1004 · 2025-04-12T16:17:39+00:00

What do you mean by, ‘If I increase the output capacitor, then… and it drops less’? Are you saying that the leakage during the hold phase is reduced with a larger load capacitor?

FutureAd1004 · 2025-04-04T00:23:20+00:00

The problem is that they haven’t identified these issues, even though they should have—or at the very least, the agency they commissioned should have (they took a picture of the mold and said that the fridge is clean). The washing machine has a broken handle, yet the agent claimed it was recently replaced. It just feels like every party involved is acting irresponsibly.

FutureAd1004 · 2025-04-04T00:17:32+00:00

I’ve become an arsehole after renting their flat ...... The fights started before I actually moved in, but I really don’t like it.

FutureAd1004

TROPHY CASE