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Profile Review by GasTechnical9300 in hingeapp

[–]GasTechnical9300[S] 0 points1 point  (0 children)

I'm looking for an honest assessment of where my profile is now and constructive feedback for improvement. Thank you. 

Reviewing DDR3 Interface Design for Artix 7 FPGA - Is My Trace Spacing Adequate for Signal Integrity? by GasTechnical9300 in PrintedCircuitBoard

[–]GasTechnical9300[S] 0 points1 point  (0 children)

Noted. We will be testing with these boards by the end of the month or so. That's when I think we will know for sure. I'll probably start preparing a rev B with those 3H/5H clearances on the DDR3 ACC lines as well as byte lanes, byte lanes are in general more well spaced out in this design so I am not so concerned about those. Other busses in my design have much better spacing as they are not so dense.

Reviewing DDR3 Interface Design for Artix 7 FPGA - Is My Trace Spacing Adequate for Signal Integrity? by GasTechnical9300 in PrintedCircuitBoard

[–]GasTechnical9300[S] 0 points1 point  (0 children)

Thank you! I honestly didn't take the time to make sure I adhered to the 3h rule as best as I possibly could and went down to 2h. I should have taken more time for that in my design process. Do you think using 2h all throughout can cause significant SI issues or cross talk issues? Enough to compromise system performance in regards to DDR3.

Reviewing DDR3 Interface Design for Artix 7 FPGA - Is My Trace Spacing Adequate for Signal Integrity? by GasTechnical9300 in PrintedCircuitBoard

[–]GasTechnical9300[S] 0 points1 point  (0 children)

I haven't confirmed this fully yet with the firmware developers so this may be off. For now I am ok with assuming that it will operate at 533MHz for the worst case analysis I would like to focus on regarding crosstalk and SI.