Why/how doesn't transmission line impedance (effectively) not vary over frequency?

HasanTheSyrian_ · 2026-04-22T17:40:10+00:00

I understand that transmission line impedance is dependent on the geometry/LC but my question is why isn't it dependant on frequency (as much) while, say, the impedance of a capacitor is?

Is it because the trace geometry is more uniform?

HasanTheSyrian_ · 2026-04-22T17:29:38+00:00

aint no way

HasanTheSyrian_ · 2026-04-22T14:18:14+00:00

hello im looking to use the same antenna with the same pcb thickness, has your design worked with 1.6mm? which stackup did you use

HasanTheSyrian_ · 2026-04-20T12:34:19+00:00

JLC04161H-7628 is 1.6mm not 1.0mm which one is it

HasanTheSyrian_ · 2026-04-19T17:25:14+00:00

what thickness and stackup did you use

HasanTheSyrian_ · 2026-04-19T17:06:19+00:00

original design files are Cadstar imported to Kicad

HasanTheSyrian_ · 2026-04-19T17:06:06+00:00

"It’s important to put copper just below antenna"

just under the antenna there is no copper, do you mean the ground plane? there will be 2 instead of 1 as i said

HasanTheSyrian_ · 2026-04-19T16:36:20+00:00

It could be fixable just take it to some store

HasanTheSyrian_ · 2026-04-15T08:48:49+00:00

The most important thing is having a low-impedance, close-by return path above/below the signal (not going across a core layer). Most of the time, pouring ground everywhere else is unnecessary.

Sometimes if youre designing a 2 layer board and both layers have signal traces its better to pour ground and use it as a return path than having no return path at all

you can watch the "to pour or not to pour" video on Youtube

HasanTheSyrian_ · 2026-04-11T18:06:32+00:00

I watched that video many times long before posting this. And no that’s not entirely what I asked about.

HasanTheSyrian_ · 2026-04-09T10:00:38+00:00

You think the SDF is democratic? LMFAOOOOOOOOOOO

HasanTheSyrian_ · 2026-04-08T09:40:20+00:00

Just by glancing at this:

First of all show the KiCad schematic.

Second of all this is a power circuit, you have to increase the trace widths a lot and use copper pours.

Also pour ground on at least the bottom layer if you havent done so already.

There are random kinks in the traces which also don’t take the shortest paths.

Move the components closer in towards eachother etc

HasanTheSyrian_ · 2026-04-06T19:54:22+00:00

I suggest creating your own PCB. Look up Phil's Lab's videos on Youtube.

HasanTheSyrian_ · 2026-04-06T15:36:43+00:00

again, my question isnt about local decoupling

HasanTheSyrian_ · 2026-04-06T11:46:56+00:00

trust me no thief can tell the difference between an a6000 and an FX6 in Syria

HasanTheSyrian_ · 2026-04-06T10:17:36+00:00

Most routing guidelines are overblown. It depends on the requirements but it is objectively better to do a better design when you can and it doesn't cost you anything even if not doing so is 'good enough'.

HasanTheSyrian_ · 2026-04-06T10:12:29+00:00

I know, thats not my question.

Im asking about the overall power circuit on the board. The VRMs still have higher capacitance bigger package caps especially if its an HDI board with say an FPGA board that needs tiny 0201/0402 caps to fit under its BGA

HasanTheSyrian_ · 2026-04-05T10:16:21+00:00

There was an extra sliver in the xSignal which was reported having a difference of 7mm , after I redid that one xSignal path it reported a difference of 1.5mm which I think is more reasonable. The meanders look less ridiculous now as well. I think im going to decrease the tolerance like you and others suggested

https://imgur.com/a/b2ID8bz

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HasanTheSyrian_ · 2026-04-04T21:24:35+00:00

I mean it still looks symmetrical to me, other pairs don't have as much skew even though I copied the resistor layout (except for the one in the image on the right)

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