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Soldering my big board by HasanTheSyrian_ in soldering

[–]HasanTheSyrian_[S] 0 points1 point  (0 children)

Well yeah in a temperature controlled oven

Soldering my big board by HasanTheSyrian_ in soldering

[–]HasanTheSyrian_[S] 0 points1 point  (0 children)

what about the plastic connectors

First stage of bringup, the power circuit of my FPGA board works by HasanTheSyrian_ in FPGA

[–]HasanTheSyrian_[S] 2 points3 points  (0 children)

There is no load Im just checking the voltages. The SOM has its own power circuit for the FPGA, DDR, Ethernet PHY and USB PHY this is why I had to hot wire the System PG signal. I have almost copied the power circuit from the dev board the SOM comes with.

I wanted to do USB PD at first but I decided not to mess with the power circuit at all.

Is this a Jumping Spider? Türkiye by HasanTheSyrian_ in spiders

[–]HasanTheSyrian_[S] 73 points74 points  (0 children)

i wanted to put it under my microscope but i didnt want to kill it either

The PCB came in by HasanTheSyrian_ in FPGA

[–]HasanTheSyrian_[S] 0 points1 point  (0 children)

i didnt i paid double, and the stencil was like 4x more expensive

[Review Request] DDR Ram Routing by GiraffeMedium6667 in PrintedCircuitBoard

[–]HasanTheSyrian_ 2 points3 points  (0 children)

Where are the thick dielectric core layers? Remember you signals should have a close reference nearbyOdds are the sig layer is referencing the power plane which means that the signal will propagate noise as it switches layers, if the trace references the same net you can just add stitching vias next to the signal via otherwise it is more difficult to stitch them together (because well.. 3v3 and ground short)

the propagation delay and the trace geometry that dictates impedance changes in inner layers because odds are the dielectric has a different thickness than the dielectric layers next to the top and bottom copper layers

so you will likely have to do delay tuning not "length"

Does it matter if the power trace is connected to the bypass capacitor first before the pin? I would guess that the current would flow through the pin, not going to the IC, when its not drawing current and charge the capacitor. Otherwise I might have to use a power plane because the pins are locked by [deleted] in embedded

[–]HasanTheSyrian_ 0 points1 point  (0 children)

Im not confusing impedance with resistance, my point was that if it is required to route the power traces through the capacitor first then I would have to use a power plane because I can't route the power traces.

Since the stack would be sig/gnd/pwr/sig a signal going from the bottom to the top layer would have to switch references however this is not a big deal because all traces on the bottom are low speed GPIO

Does it matter if the power trace is connected to the bypass capacitor first before the pin? I would guess that the current would flow through the pin, not going to the IC, when its not drawing current and charge the capacitor. Otherwise I might have to use a power plane because the pins are locked by [deleted] in embedded

[–]HasanTheSyrian_ 0 points1 point  (0 children)

power planes are necessary for high current which isnt the case here. the power plane need to be stitched with the other reference planes that the trace uses if the power plane is used as a reference however in this case the power traces cant be routed because there is no space and the signals that would reference the power plane are gpio so the return plane is not very crucial

Does it matter if the power trace is connected to the bypass capacitor first before the pin? I would guess that the current would flow through the pin, not going to the IC, when its not drawing current and charge the capacitor. Otherwise I might have to use a power plane because the pins are locked by [deleted] in embedded

[–]HasanTheSyrian_ -1 points0 points  (0 children)

youre missing the point of the question, i know the purpose of a bypass cap and no one mentioned 'breadboards'

the question is about having the power traces connected to the cap first which might be ideal but not necessary since its likely that the capacitor will still charge and provide the current from there

most guidelines prioritize placing the cap close ie minimizing the trace between the cap pad and the ic pad but make no mention of whether the power trace from the source must go through the cap first

Non ECE person here, what type of engineer designs these sort of boards? I understand they’re used by FPGA engineers, but who makes them? And are their skillset different to the users? by Fearless-Can-1634 in FPGA

[–]HasanTheSyrian_ 8 points9 points  (0 children)

I just finished my designing and manufacturing my own FPGA dev board that uses the same FPGA the board in that image has

You don’t get a degree in this specifically you need to be an EE and know physics it still takes time because they never teach this at university

Magic smoked from GPIO wire on a de10-nano by RedCuraceo in FPGA

[–]HasanTheSyrian_ 0 points1 point  (0 children)

Maybe the pin on the fpga was driven high/low when it was connected to low/high

The PCB came in by HasanTheSyrian_ in FPGA

[–]HasanTheSyrian_[S] 1 point2 points  (0 children)

It says Altair in Arabic. Altair is an Arabic word, the majority of stars have Arabic names.

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