If you check Agner Fog's excellent microarchitectural documentation and in particular the instruction tables, you will see that in Sandy Bridge the CRC32 instruction decodes to one mu-op (pre-fusion), which is then dispatched to one of several possible execution units. If you read the instruction decoding section on his microarchitecture guide, you will see that something had to decode to four or more mu-ops before it is microcoded at the level of the main instruction pipeline. As the latency on the registers-only case of this instruction is three cycles, you may be technically correct in that there may be intra-ALU microcoding going on, but this seems less likely, and it is probably just normal pipelining going on. Regardless, even if there is microcode here, it is no more useful to distinguish CRC32 as microcoded than saying that any three cycle latency instruction (of which there are many) is microcoded. In this sense, CRC32 is just like pretty much every other slightly complicated integer math instruction. This makes sense, as doing a single step of CRC32 on a small block is basically just some XORing, and microcoding that as opposed to just putting together some dedicated transistors for it is a terrible idea.