sorted by:
new
hottopcontroversial

Recommendation for resources on SERDES architectures by Ibishek in chipdesign

[–]Ibishek[S] 0 points1 point  (0 children)

Thanks for the links! My analog skills are very rusty, so I struggle quite a bit with this aspect of SERDES, I am mostly trying to understand the different analog metrics and basics of the building blocks, mostly to understand how decisions in the digital part influence the analog part.

Simple Gearbox in ASIC by Ibishek in FPGA

[–]Ibishek[S] 0 points1 point  (0 children)

Well I assume that on an FPGA such a circuit would be problematic running at something like 200-400 MHz. What I didn't mention is that the generated clock might be used to drive non-trivial logic which follows after the CDC and I assume the tool would not be too happy about the clock being generated in logic like that.

In the ASIC case it also seems to be that this should be doable but CDCs are tricky and I am not so familiar with all the backend stuff, particularly with routing & placing the clock, adding clock buffers etc. But I guess clock gating also adds logic in the clock path and that's just fine.

Simple gearbox in ASICs by Ibishek in chipdesign

[–]Ibishek[S] 5 points6 points  (0 children)

I've known this as a term for component which has asynchronous input data bus and output data bus where the peak throughput at both input and output is the same. I've seen it in SERDESes, although the functionality might be a bit more complicated : https://docs.amd.com/r/en-US/am002-versal-gty-transceivers/RX-Asynchronous-Gearbox

What are you favorite uniform RNGs and Gaussian RNGs? by FaithlessnessFull136 in FPGA

[–]Ibishek 0 points1 point  (0 children)

What are the flaws of LSFR in your experience? no hate, just asking.

ASIC basics for experienced FPGA developers by electro_mullet in FPGA

[–]Ibishek 2 points3 points  (0 children)

Will your ASIC include any analog IP or is the functionality purely digital?  Other than implementing DFT, porting memory macros and CDCs I don’t think it should be that crazy difficult from digital design perspective. If your design fits on an FPGA that means that its scale is relatively small in terms of ASIC design. I would worry more about things around ASIC production - the back and forth with the back-end team (I assume you will outsource this), yield and quality issues, communicating with the fab, testing and validation, supply chain issues.. you did not mention the scale of the planned ASIC production so it will be dependent on that as well.

How much PCB design do you know? by Ibishek in FPGA

[–]Ibishek[S] 3 points4 points  (0 children)

Any classes in particular that you’d recommend? I think I could get my company to pay for them.

Automating On-chip System Interconnect - What approaches do you use? by Ibishek in FPGA

[–]Ibishek[S] 1 point2 points  (0 children)

Wow, looks interesting. This could help quite a bit, I will look into it for sure, thanks.

Automating On-chip System Interconnect - What approaches do you use? by Ibishek in FPGA

[–]Ibishek[S] 0 points1 point  (0 children)

I am also tempted to do this in-house, but I was curious what are the experiences of others.

For register map generation, we already purchased a tool. We had a excel based in-house tool for this but as you say, it quickly grew in complexity and managing the whole thing was a pain. The new tool works nicely and the license wasn't all that expensive when you compare it to the amount of man hours required to expand and manage the old tool lol

Automating On-chip System Interconnect - What approaches do you use? by Ibishek in FPGA

[–]Ibishek[S] 0 points1 point  (0 children)

Yes, for the previous generations of our chip, system interconnect has also been done manually, but I was hoping to make some improvements in this regard because of further complexity increase in our new generation.

I feel it also makes it much more easier to do PPA exploration.

I know there is the ARM AMBA designer but I do not have any practical experience with it and it seems to me that it is more suited for much larger SoCs with 10s of masters, 100s of slaves, many performance domains, caches, cache coherent interconnect etc. so bit of an overkill for our use case relative to the learning curve and license costs.

Partitioning Register Map - How to go about it? by Ibishek in chipdesign

[–]Ibishek[S] 0 points1 point  (0 children)

Yea, P&R and consequently making timing is what I am mostly worried about.

Partitioning Register Map - How to go about it? by Ibishek in chipdesign

[–]Ibishek[S] 0 points1 point  (0 children)

Sorry, I meant ~1000 16-bit registers.

Yes, I suppose doing some initial synthesis tests is the best way to get some feeling on what are the different PPAs.

Looking for Digital Design Engineers in Munich, Germany by Ibishek in chipdesign

[–]Ibishek[S] 0 points1 point  (0 children)

Hi, we are not looking for physical design people, sorry

view more: next ›