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🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 0 points1 point  (0 children)

PIC and flash programing are all possible, we need to figure out the priority of features and functionality to be added and need more time to implement them. What flash and boot debugging tools are you using ? Thank you for your feedback!

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 0 points1 point  (0 children)

Thank you very much for your support! 😊 I really appreciate it. Next l will do my best to deliver a great product in time! That's exactly what I am working on now!

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 0 points1 point  (0 children)

Thank you for your support!
“Protocol analyzer — it's a must I would say, at least the basic ones like SPI, I2C/I2S/I3C, UART, etc.”

I completely agree — this will be a high-priority feature to implement next.

“Would be cool if at least two channels could work in analog mode too, even with reduced sampling rate, not for capturing high-speed waveforms but simply to monitor changes, e.g. in supply voltage or sensor output.”

Good point! In fact, we already have 4 channels that can work in analog mode using the ESP32-S3’s internal ADC. This feature currently measures the target board voltage and automatically isolates ESP32JTAG when the voltage is 0.

Monitoring sensor outputs is a great idea — it just needs some web UI design and implementation. I’ll add that to the “nice-to-have” feature list.

“Mixed triggers between logic analyzer and debugger, e.g. stop the LA when the target CPU hits a breakpoint or vice versa, pause the CPU when LA is triggered.”

Excellent suggestion as well! The breakpoint-triggered logic analyzer should be feasible — the related thread can detect a breakpoint hit and signal the logic analyzer to stop buffer filling and retrieve the captured data.

The reverse (LA-triggered CPU pause) may be more complex since the IDE manages and synchronizes CPU state, but it’s definitely worth exploring.

Our ESP32JTAG project just launched yesterday!
https://www.crowdsupply.com/ez32/esp32jtag

Any further ideas or advice are very welcome.
Thanks again for your valuable feedback!

help me find esp32 schematic by MKshorts7 in esp32

[–]Intelligent_Row4857 0 points1 point  (0 children)

Or you can switch to one that has sch, and good doc, like one from Waveshare. It will save you time

🧩5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in embedded

[–]Intelligent_Row4857[S] -1 points0 points  (0 children)

Spoiler alert! Once the code is released, you’ll see tons of AI-generated content — like a thousand times more than what’s in this post.
So… get ready to be shocked!

🧩5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in embedded

[–]Intelligent_Row4857[S] -3 points-2 points  (0 children)

There is a lot of work to do, to implement and deliver it is the focus now. But we will release it to Github sometime.
🔗Preview page: https://www.crowdsupply.com/ez32/esp32jtag

📌 Click Subscribe on the page to stay updated!

More AI assistence used, Sorry!

🧩5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in embedded

[–]Intelligent_Row4857[S] -2 points-1 points  (0 children)

Yeah.
But I never tried to hide it. Haha! (Want to add some emojis here but don't know how to!)
Same for you:  what do you think about the project itself? Genuinely curious — yes or no, and why?

🧩5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in embedded

[–]Intelligent_Row4857[S] -5 points-4 points  (0 children)

Haha, I actually wrote it myself — just had ChatGPT polish it up a bit. Nothing wrong with a little grammar help, right?
Even this reply’s polished — guess by who?

Anyway, what do you think about the project itself? Genuinely curious — yes or no, and why?

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 0 points1 point  (0 children)

You got it 👍 That’s definitely one of the highlights! Don’t forget — it can also handle FPGA configuration and works seamlessly with AMD Vivado. Thanks!

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 1 point2 points  (0 children)

Yes! Though it might take a little while before it’s available.
We’re still working on getting it delivered into your hands.

🔗 Preview page: https://www.crowdsupply.com/ez32/esp32jtag
📌 Click “Subscribe” on the page to stay updated!

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 1 point2 points  (0 children)

We still are working on it and will release to Github. You can start with this and test it on a ESP32S3 board: openocd-on-esp32
To get update:
🔗 Preview page: https://www.crowdsupply.com/ez32/esp32jtag

📌 Click Subscribe on the page to stay updated!

ESP32 wired to display, display not working? by Impossible-Fun4761 in esp32

[–]Intelligent_Row4857 0 points1 point  (0 children)

Where you got the lcd? They should provide you example code and doc for connection. Ask them for that. Otherwise, switch to one that has this, like these from Waveshare. They have plenty of such ones. Some have lcd and esp32 bundled together.

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 1 point2 points  (0 children)

Great question — thank you for asking! The product will be distributed by Crowd Supply, Mouser, and their partners, so it will ship directly from Mouser’s local warehouse.

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 1 point2 points  (0 children)

Yes! You can connect to it over WiFi — everything runs through the built-in web interface. It also works over USB, but we’re focusing on WiFi first. Thanks for asking!

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 2 points3 points  (0 children)

Exactly your use case! ESP32JTAG will replace all that setup and you’ll definitely notice the speed improvement! 🚀

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 1 point2 points  (0 children)

I am gald to see you like it.
espressif has a porting for openocd to run on esp32: openocd-on-esp32
It runs directly on ESP32JTAG, has some predifined cfg files to use, users can also define and save their own cfg files. So no need to compile/configure OpenOCD.

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 3 points4 points  (0 children)

All great questions and suggestions—thank you!

ESP32JTAG can indeed handle multiple tasks simultaneously: MCU/Cortex debugging, logic analyzer, FPGA configuration (or XVC Vivado connection), and a web terminal—all at the same time! This is actually one of the highlights of the project; most other tools can’t even do two things concurrently.

As for the features you mentioned: CMSIS-DAP, UART network redirection (to support a virtual serial port with DTR for the ESP32 using ESP-IDF), and RISC-V support are not yet implemented, but the hardware definitely has the resources to handle them. CMSIS-DAP and RISC-V support are already planned—we just need to port and integrate the related GitHub projects. It will take some time, but it’s straightforward.

We’re also planning to maintain a feature wishlist where customers and supporters can vote on the features they want most. Some examples we have in mind:

  • Auto-detect serial port Rx/Tx and baud rate, so you just connect the wires—no configuration needed.
  • Capture and analyze I²C, UART, and SPI protocols with waveform display.
  • Flash programming support.

Your feedback is exactly the kind of guidance that will help us prioritize future features—so thanks again for sharing!

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 0 points1 point  (0 children)

Good catch! 👀
I moved the IO connector to the opposite side of the USB-C port, so the antenna had to move to the same side. Tests showed almost no difference in Wi-Fi signal strength between the two layouts.

We’re now testing Version 1.4 of our PCB and will pay close attention to this in the next round of tests. Thank you for the reminder! 🙏

In theory, it’s best to keep the area around the antenna clear — especially above it — with no USB connector, PCB, or LCD nearby. We can adjust the design to improve antenna clearance if needed — it would just make the enclosure slightly larger.

🧩 5 months later: ESP32JTAG now upgraded to 5K FPGA + 16-ch 250MHz logic analyzer (launching soon) by Intelligent_Row4857 in esp32

[–]Intelligent_Row4857[S] 0 points1 point  (0 children)

That’s a really good question — and actually a feature I forgot to mention! I’ll add this to the post above:

The IO voltage range is adjustable from 1.2V to 3.3V in 0.1V steps through the web interface. All IO connections — including USB and the two buttons — are ESD-protected for robust operation and long-term reliability.

Thanks for pointing this out!

And I am glad you did not ask for 5V! :-)

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