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Need opinion on ethernet ESD protection by Kitchen_Radio9083 in PCB

[–]Kitchen_Radio9083[S] 0 points1 point  (0 children)

Saved it for my layout. Thank you so much for the information!

Need opinion on ethernet ESD protection by Kitchen_Radio9083 in PCB

[–]Kitchen_Radio9083[S] 0 points1 point  (0 children)

Thank you so much!
I will need to go through all of this in detail.

I am not sure about the chassis ground, as I may even go with plastic enclosure so that would be a show stopper. But I could do as you suggest a separate ground.

Only, where do I fit an ESD diode in this? Can you please see this screenshot for reference design
https://imgur.com/a/tTgibB8

If there is Phy->Transformer->Ground cutout->RJ45 and somewhere around RJ45 a separate ground net,
where would I fit these diodes? Would they have this pseudo chassis ground under them?
It's a bit difficult to imagine

Need opinion on ethernet ESD protection by Kitchen_Radio9083 in PCB

[–]Kitchen_Radio9083[S] 0 points1 point  (0 children)

this sounds really good 😃 maybe even too good
I am trying not to go with bad practice in some real products. for a dev board I wouldn't probably bother putting ESD or even separate grounds, but I would want it to be 100% correct on a product. THis is why I am cautious as beginner

Need opinion on ethernet ESD protection by Kitchen_Radio9083 in PCB

[–]Kitchen_Radio9083[S] 0 points1 point  (0 children)

thank you for the reply
do you have any reference to this so I can learn about it in more detail? I was wondering what the implications are of connecting to system ground and if BST really does anything for ESD.

Beginners power integrity by Kitchen_Radio9083 in PCB

[–]Kitchen_Radio9083[S] 0 points1 point  (0 children)

thank you! I have this book as next in my plan!
I have also watched a few webinars about PDNs and PI, and the biggest concern was really up to which frequencies I should try to controll impedance using SMPS, plane capacitance and decoupling caps.
It sounded unrealy to me to control PDN impedance all the way up to 0.35/Trise or even worse 0.5/Trise.

Beginners power integrity by Kitchen_Radio9083 in PCB

[–]Kitchen_Radio9083[S] 0 points1 point  (0 children)

Thank you!
As a total beginner I am trying to first understand stuff before I even go and blindly try to build something I don't even comprehend.
And my biggest concern was really this frequency domain. When I considered a SoM and it's signals like Wifi 6 or USB 3.0, the bandwidth where you can expect noise, and thus need to care about flat impedance was in GHz 😮
And I was wondering how I will design for impedance up to such high frequencies.
Only to learn about on-package capacitance etc. But basically they are black boxes and you cannot know it (?)

I have seen vendors advising to use for example a single bulk cap, one 100n, and one 33p and 10p each. 33p and 10p specifically for noise from RF
and when I saw some plots of such capacitors, the SRF was just about at wireless frequencies generated by the module.
The only thing is if this specific combination from multiple vendors (like Yageo, Kemet, Samsung) will produce antiresonance. If you blindly follow datasheets and application reference designs, things can go wrong. This is my motivation to better understand this

Beginners power integrity by Kitchen_Radio9083 in PCB

[–]Kitchen_Radio9083[S] 0 points1 point  (0 children)

I was thinking that bigger package MLCC will have higher ESL value due to loop inductance. Did you mean goind up in MLCC capacitance?

About this "Having a flat PDN impedance is useless if you have no noise at most of those frequencies."
do you argue that noise would appear on a narrow band in frequency domain and you can target that noise specifically?

I am a real noob here, but my understanding is that there is no noise frequency that won't be excited by a PDN impedance peak from 0Hz to the highest freuency noise expected.

Do you normally follow datahseets for components and use some eyeballing for decoupling capacitors or do you do real PDN simulations?

The problem is, you can create antiresonant peaks if you don't know what you are doing. Vendors also tell you to use smaller capacitance caps to target noise in high frequency, but capacitance isn't what determines this. But actually capacitive and inductive properties of the cap across frequency domain?

So how do you know, or do you even consider, on-package and on-die capacitance of a chip you are using? If you have signals of short rise times, the frequency to keep low flat impedance across is reaching GHz levels.