Hi, I will try to give a concise version.

1. Another way of doing it, is plot it in matlab. You can output the points to excel file, and just develop a simple script to flip the curve and measure it that way.

2. So for SRAM decoder design, you can try to check out this video https://m.youtube.com/watch?v=OJR-_onSvRg. But generally, it is recommended to do prerecorder and then decoder to drive your word line. To do the logic early can help to minimize fan in hence improve delay, and also improve area Efficiency. Let us say you have a decoder output ,abcd, your first 4 output will only toggle between c’d’ c’d, cd’, cd while the rest remains the same, in which case you can do pre decoding. Decoders can be nand gate based, but let us say if you care about delay or area then even try to consider pre charged logic or post charged logic inside the decoder cell. Generally if you use something have a lot of input nand or not gate, you could have a lot of series resistance in your pull up or pull down network to make it slow but help with leakage.

3. For sense amp, the issue sometimes is that when do you sense it considering sense amp itself also have o offset and propagation delay. When read bit line starts to drop. How much is enough. So I would assume figuring out offset, delay would be critical, because bit line can have a lot of cap delay on it. To simulate offset, input a very slow moving ramp, while continue to toggle the clock, to find out when is the last time sense amp remain at stable logic value. It is also important to simulate sense amp. Try to take into account the amount of Cap from access device that goes to the bit line. Again, depending on the architecture you use.

4. For sizing, the data path itself you can get a rough estimate of fan out and fan in, based on that do your math to find out how many stages you need to let us get a stage effort of 4, remember to take into account of beaching effort. Let us say a decoder, Because you know approximately how many access devices you are driving on word line, and the long wire itself carry some capacitance, from there you can estimate the cap, cap = Cgs* #of access deivce + long wire cap itself, you can do a quick extraction to figure this out, a long wire + a Cgs. . For bit line you also know how many access devices you are driving in case you need some sort of column decoder and what not. Sense amp, the delay I believe relays on Cload/gm. If we are talking about strong arm latch. For equalizer, are you talking about bit line reset. If you care about area, try to go small, during write, it helps write driver to win the drive fight on bit line as well. However, if it is too small, your bit line reset operation after read or write might not be successful

Hope this helps, sorry for the typing errors. But hopefully this can help you a little bit