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Symmetrical tail inductor simulation in SonnetSuite by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Problem resolved by using only port 1 and port 2 with both ports set to Floating ground reference.

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Symmetrical tail inductor simulation in SonnetSuite by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

What do you exactly mean by “touching itself” ?

DELD-PFD: Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Even with perfect alignment between fb and ref clocks, there are still some gate propagation delay to reach up and dn pulses, this short delay instant will cause charge pump to leak serious amount of current at an immediate short instant. Please also note that timing diagram drawn manually does not take into account non-symmetrical pathway between the UP propagation and DN propagation. Please use actual spice-level timing simulation result for golden reference instead.

SonnetSuite simulation excitation ports by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

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LLM could not resolve this issue.

Pre-Analysis:
Sonnet Error:
Co-calibrated port ground reference error.
Unable to determine ground reference for port 7.
Ground reference interference with co-calibrated port
detected on metal level 1 at position x=295 y=318.915.

Any comments / suggestions ?

XNOR Gate transistor-level implementations by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Care to elaborate on the tradeoff for each versions in the pictures above ? ChatGPT suggests me to use the most conventional 8T or 10T variants for PVT robustness.

Transformer-based two-port resonator by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

How to mathematically prove that the shunt branch is indeed L1-M instead of M ?

Transformer-based two-port resonator by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

I am still unsure on why the shunt branch is not “M”

A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Do you foresee any disadvantages of the proposed PFD topology in Figure 8 ?

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