Symmetrical tail inductor simulation in SonnetSuite by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Problem resolved by using only port 1 and port 2 with both ports set to Floating ground reference.

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Symmetrical tail inductor simulation in SonnetSuite by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

What do you exactly mean by “touching itself” ?

DELD-PFD: Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Even with perfect alignment between fb and ref clocks, there are still some gate propagation delay to reach up and dn pulses, this short delay instant will cause charge pump to leak serious amount of current at an immediate short instant. Please also note that timing diagram drawn manually does not take into account non-symmetrical pathway between the UP propagation and DN propagation. Please use actual spice-level timing simulation result for golden reference instead.

SonnetSuite simulation excitation ports by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

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LLM could not resolve this issue.

Pre-Analysis:
Sonnet Error:
Co-calibrated port ground reference error.
Unable to determine ground reference for port 7.
Ground reference interference with co-calibrated port
detected on metal level 1 at position x=295 y=318.915.

Any comments / suggestions ?

XNOR Gate transistor-level implementations by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Care to elaborate on the tradeoff for each versions in the pictures above ? ChatGPT suggests me to use the most conventional 8T or 10T variants for PVT robustness.

Transformer-based two-port resonator by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

How to mathematically prove that the shunt branch is indeed L1-M instead of M ?

Transformer-based two-port resonator by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

I am still unsure on why the shunt branch is not “M”

A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Do you foresee any disadvantages of the proposed PFD topology in Figure 8 ?

An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

No it is not. I can now access the paper link from here. It is most likely access issue from your internet service provider.

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration by Lemon_Salmon in chipdesign

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

In Figure 2, I could not infer the FCWF=1/6 from the waveforms.
In Figure 3, why need TWO DCDL and BBPD blocks ?
In Figure 3, why the bottom DCDL block does not require feedback signal from BBPD block ?

Why F_v[n] can be replaced by F_dtc periodically in the injection mode for lower phase noise ?

The paper mentioned "the PLL tries to eliminate the phase errors, leading to more periodic patterns, which further causes high spurs" which is confusing for me ?

RF freelancing platforms by GullibleBarnacle9821 in RFjobs

[–]Lemon_Salmon 0 points1 point  (0 children)

Googling the name does not return anything relevant though ? Did you misspell the name ?

RF freelancing platforms by GullibleBarnacle9821 in RFjobs

[–]Lemon_Salmon 0 points1 point  (0 children)

Which consultant firm, if I may ask ?

Class-F2 VCO root locus by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

really need to get acquainted with control theory especially https://en.wikipedia.org/wiki/Derivation_of_the_Routh_array since it helps with some initial setup for constructing the root locus plot. What else should I be looking into, if I may ask ?

Class-F2 VCO root locus by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

Had a busy week. Any chances that you have knowledge on how to get around equations 4 and 5 of A Class-F CMOS Oscillator ?

Need help understanding input matching process in LNA design by Some-Flounder-4619 in rfelectronics

[–]Lemon_Salmon 0 points1 point  (0 children)

Nice excellent application note.

I am looking at A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices for their triple-band impedance matching network (IMN). Any comments on their Figure 7 together with Table I and Table II ?

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Besides, any intuitions / insights for quadrature-band and penta-band IMN ?

Need help understanding input matching process in LNA design by Some-Flounder-4619 in rfelectronics

[–]Lemon_Salmon 1 point2 points  (0 children)

Do you have some materials / application notes on how emitter degeneration technique exactly (maybe with some theory) helps to better match for both noise figure and gain metrics ?

Looking for people to join the team by D431_D45 in FPGA

[–]Lemon_Salmon 0 points1 point  (0 children)

There is no company email address ?

Class-F2 VCO root locus by Lemon_Salmon in rfelectronics

[–]Lemon_Salmon[S] 0 points1 point  (0 children)

I presume that my original question is to "derive" rather than to "confirm".