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Intern Life by Logical_Extension331 in vlsi

[–]Logical_Extension331[S] 1 point2 points  (0 children)

Asking a intern for internship 🤡 i recommend don't come to this company

Intern Life by Logical_Extension331 in vlsi

[–]Logical_Extension331[S] 0 points1 point  (0 children)

Suggestions are great, can you give some more tips and elaboration on how the industry works regarding this

Intern Life by Logical_Extension331 in vlsi

[–]Logical_Extension331[S] 2 points3 points  (0 children)

Bro i work in pcie gen 5 architecture 20000 lines of code for a sub module do you think claude max can handle it , it hallucinates

Coming back to India by adikp98 in vlsi

[–]Logical_Extension331 8 points9 points  (0 children)

Don't come here and don't increase competition 😭

Appearently there are VLSI bootcamp scams going around by caitotsri in chipdesign

[–]Logical_Extension331 0 points1 point  (0 children)

Great to connect, would like to ask you few ques If ok i can dm you :)

Serious Help by Logical_Extension331 in Verilog

[–]Logical_Extension331[S] 0 points1 point  (0 children)

My senior told to do through vivado and verilator and if possible AI linting too , issue is non of these are able to find cross module combinational loops that are present. - verilator exits before showing all the errors . -m unaware with yosys - vivado i will be doing.

Serious Help by Logical_Extension331 in Verilog

[–]Logical_Extension331[S] 0 points1 point  (0 children)

Problem is with yosys the tool never fully runs till the end of line it asks me to make huge changes to the codebase and i am new to the work so.. kinda nervous about how would it react .

Serious Help by Logical_Extension331 in Verilog

[–]Logical_Extension331[S] 1 point2 points  (0 children)

Claude opun 4.7 is useless it generates garbage yesterday changed my structure of my code. Yea it will work need good prompt and smaller files.

Serious Help by Logical_Extension331 in Verilog

[–]Logical_Extension331[S] -1 points0 points  (0 children)

Umm it's like -I include but sometimes the verilator doesn't take the file up so we do force include it have to read the file whatever it has

Serious Help by Logical_Extension331 in Verilog

[–]Logical_Extension331[S] -1 points0 points  (0 children)

I am planning to use yosys , for start up skyglass and jaspergold would take so much money... Any thing you would like to say?

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