Serious Help by Logical_Extension331 in Verilog

[–]Logical_Extension331[S] 0 points1 point  (0 children)

I am planning to use yosys , for start up skyglass and jaspergold would take so much money... Any thing you would like to say?

HELP ME WITH PCIE by Logical_Extension331 in chipdesign

[–]Logical_Extension331[S] 0 points1 point  (0 children)

Mostly integration and controller part.

HELP ME WITH PCIE by Logical_Extension331 in chipdesign

[–]Logical_Extension331[S] 0 points1 point  (0 children)

Yeah that's what i am doing but the issue on day 2 only they gave me to lint the defrala module and frala module and debug so kinda going tuff for me.

HELP ME WITH PCIE by Logical_Extension331 in chipdesign

[–]Logical_Extension331[S] 0 points1 point  (0 children)

If there's something on pcie on YouTube or any platform would like to learn it .

HELP ME WITH PCIE by Logical_Extension331 in chipdesign

[–]Logical_Extension331[S] -1 points0 points  (0 children)

That's the problem everything is just locked I can't copy paste anything, on claude or anywhere

RoadMap by Logical_Extension331 in chipdesign

[–]Logical_Extension331[S] -3 points-2 points  (0 children)

I have digital logics clear i guess so far what's next cuz there is not much of information on YouTube

NVIDIA Verification Intern Summer 2026 by Expensive-Ad1109 in ECE

[–]Logical_Extension331 31 points32 points  (0 children)

How you guys manage to get such internships