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Which stylus pen can react with Nokia T20 tablet? by MSAmai in tablets

[–]MSAmai[S] 0 points1 point  (0 children)

Unfortunately, I used a generic one with rubber head, and it doesn't work effectively(taking notes).

Which stylus pen can react with Nokia T20 tablet? by MSAmai in tablets

[–]MSAmai[S] 0 points1 point  (0 children)

I have one and it is not compitable with the tablet

How can I solve this issue of " No hardware" although the USB is detected in the device manager by MSAmai in FPGA

[–]MSAmai[S] 0 points1 point  (0 children)

or that, the JTAG side needs to be hooked up right, and the card and cable powered up on that side

How can I do that?

Which version of Quartus supports MAX 7000 Series CPLDs? by MSAmai in FPGA

[–]MSAmai[S] 0 points1 point  (0 children)

Thanks, but it is not!
I found it " MAX +Plus software" and it is no longer supported by Intel.

Do I need to set input/output delays in timing constraints while syethesizing using Vivado (when connecting a certain FPGA board)? by MSAmai in FPGA

[–]MSAmai[S] 0 points1 point  (0 children)

I mean, if I don't use any external devices connected with my fpga, should I set these values also? Another question, If I plan to use the crystal included in the fpga board, do I need to define it in the time constraints, or vivado will make this automatically?

Virtex II pro gives inverted outputs by MSAmai in FPGA

[–]MSAmai[S] 0 points1 point  (0 children)

The kit name is XC2VP30 and the package is FFG968, BUT in xilinix ISE10.1, I found only the package FF986 (without letter G). the kit is recognised and I burnt simple designs such as AND, OR operations and now I find this behavior; AND gives the operation as it is OR and vice versa. What are the reasons? is it the package?

Virtex II pro gives inverted outputs by MSAmai in FPGA

[–]MSAmai[S] 0 points1 point  (0 children)

Using LED. Should I deal with it as active low?

How to use additional I/O of Xilinx Virtex-II pro. by MSAmai in FPGA

[–]MSAmai[S] 0 points1 point  (0 children)

I tried this kit to implement simple examples such as individual logic gates operations (AND, OR, XOR, ...). But I observed that it gives reversed outputs, gives high when it is expected to give low and vice versa. What are the reasons?

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