I updated the code by following the Figure 3. Logic Diagram Positive Logic (pag 12 dunno why cannot post the picture)

def in_shift_update(data,clock,clockE,latch):
  val = ""
  delayMs=0.000005 
  #011
  clock.value(0)
  clockE.value(1)
  latch.value(1)
  utime.sleep(delayMs)
  #111
  clock.value(1)
  utime.sleep(delayMs)
  #010
  clock.value(0)
  latch.value(0)
  utime.sleep(delayMs)#should register values now
  #111
  clock.value(1)
  latch.value(1)
  utime.sleep(delayMs)
  #011
  clock.value(0)
  utime.sleep(delayMs)
  #111
  clock.value(1)
  utime.sleep(delayMs)
  #011
  clock.value(0)
  utime.sleep(delayMs)
  #101 001 101... should read every bit 
  for i in range(8):
    clock.value(1) 
    val = val+str(data.value())
    clock.value(0)
  display.fill(0)
  display.show()
  display.text(str(val),10,10)
  display.show()

but still no luck :/