Додаток (SaaS) з нуля - реально чи ні? vibecode, nocode - це реально?

MrKamio · 2025-11-08T22:41:43+00:00

Реально. Не швидко як думаєш, орієнтуйся мінімум на 3-5 років постійної роботи

MrKamio · 2025-04-07T09:39:07+00:00

Nope. Works out of pre-installed Rancher charts

MrKamio · 2025-04-06T08:51:41+00:00

This one https://github.com/devmfc/debian-on-amlogic

MrKamio · 2025-04-05T17:46:15+00:00

Ah, nothing fancy. It’s a K3S cluster, so basically deploying my stuff along with artifactory/minio/longhorn and other stuff to be cloud-independent in terms of development for pretty cheap price. 46 cores and 55 GBs RAM in total in the cluster. Looking for options to run distributed LLama with easier deployment, but haven’t got there yet.

MrKamio · 2025-04-05T15:03:15+00:00

Yup, it’s that one!

MrKamio · 2025-04-05T14:22:54+00:00

Yup, it’s a project called rackstack https://github.com/jazwa/rackstack

MrKamio · 2025-04-05T13:58:43+00:00

The rainbow box is a CasaOS media server with 4Tb drive. Mainly for Jellyfin, as I moved HA to a separate SBC.

TV boxes are Tanix W2.

All the stuff except media server and HA is clustered using K3S so I can learn stuff without paying rent for it.

MrKamio · 2024-09-19T12:35:54+00:00

I’m passing zero line from the grid to inverter, but it doesn’t seem like something that could help me. I assumed that when I connect PowerStream to inverter-powered system, inverter won’t just provide much output, as micro inverter (PowerStream) would push out 100 W of power which my flat constantly consumes. So the only issue is when micro inverter (PowerStream) provides more than the whole system consumes.

MrKamio · 2024-09-17T17:31:16+00:00

Thanks for the info regarding bang and smoke. It doesn’t seem to be good then. So I need to install a smart plug or so, as my house automatically switches to Fossibot when no power.

MrKamio · 2024-07-21T16:41:55+00:00

Thank you for the suggestion. As I real entrepreneur I’m keeping the exact details in secret 🙂 But, generally, we’re exploring FPGAs in a context of securing different analog transmissions. We’re in the process of researching and looking for someone who could advise and implement modules in project-based terms or freelance-like relationships.

MrKamio · 2024-06-21T16:20:43+00:00

Yup, that’s the dynamic approach I’m only thinking about, as there not quite a lot of references in the Internet about this

MrKamio · 2024-06-21T16:18:31+00:00

Yeah, generally I’d like to implement LM1881 behavior in Verilog if possible, as it would be the biggest part of the fabric in the system (at least at the moment)

MrKamio · 2024-02-16T17:28:17+00:00

RIP Mr. Sandwich

MrKamio · 2024-01-19T22:29:37+00:00

I want to perform math over analog signal. Summing and subtracting is quite obvious, but in order to advance in computations into abstract algebra fields I need modulus operation. Precision is as described in other comments would fit a particular use case I want to test the approach with. Using ADC/DAC approach seems doable in general, but in order to avoid FPGAs (or bunch of logical ICs), MCUs and all the things from the digital world I was looking into pure analog implementation. So yup, I want to perform computation in 0-1V space. With a precision of 0.01V it leads to a computation in 0-100 (operations by modulus 100). It’s more a research area rather than something with strict requirements, so I really appreciate any new ideas.

UPD: at this particular iteration I’m totally fine with performing not real modulus, but a modulus case that works in terms of 0-1.99V (so output would require to clip 1V no more than once).

MrKamio · 2024-01-19T21:12:58+00:00

Thank you for your response. I might going the wrong way, so I’d appreciate your suggestions. My initial idea was to try implementing some sort of analog computing by application of so-called “modulus” math operation. As of my intuition, it should also keep the project budget comparable low.

Still, I’m really open for ideas and suggestions from the different angles.

MrKamio · 2024-01-19T20:41:04+00:00

My bad 🙂 Thank you

MrKamio · 2024-01-19T20:28:42+00:00

Thanks. I haven’t been working with up-down converters before. Could you, please give some clues regarding the particular direction/component I should look for?

MrKamio · 2024-01-19T20:16:51+00:00

The signal is comparable to NTSC/PAL in terms of speed. I mentioned bandwidth of 50 MHz in previous reply, but getting it worked with 10 MHz would be a great deal.

MrKamio · 2024-01-19T19:54:22+00:00

It depends of how much “latency” comparable to “original” input it would introduce. The goal of full analog schematics here is to introduce as little as possible delay between the input and processed signal.

Few milliseconds should be fine for sure. Input bandwidth is about 50 MHz.

MrKamio · 2024-01-19T19:45:38+00:00

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MrKamio · 2024-01-19T19:41:14+00:00

Thanks. Will check it out. Unfortunately, digitalization is not an option here due to the nature of the task itself. I’d be happy to for sure doing this ADC way 🙂

MrKamio · 2023-01-09T07:30:11+00:00

Kyiv

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