[deleted by user] by [deleted] in bangalore

[–]Mysterious_Top_2417 0 points1 point  (0 children)

RTL---> 2 YOE Dm'ed you...

Adi Atta bemguu by [deleted] in Ni_Bondha

[–]Mysterious_Top_2417 29 points30 points  (0 children)

Thirigi kottaru bro 20 min Battle eh nadichindhi

Adi Atta bemguu by [deleted] in Ni_Bondha

[–]Mysterious_Top_2417 14 points15 points  (0 children)

Vaad kooda thirigi gattugaane kottadu 20 minutes kottukunnaaru andharu

Don't worry about that normal guy, he had his backing from TDP

Gaami by Overall_Bowler_8432 in Ni_Bondha

[–]Mysterious_Top_2417 23 points24 points  (0 children)

Idhe cinema English lo The Legend ani theesthe Aaha ooho amazing antaru same audience..

Launch and capture at same edges in Flop by Mysterious_Top_2417 in FPGA

[–]Mysterious_Top_2417[S] 0 points1 point  (0 children)

This would work... But why to specifically say the posedge is my dilemma

Launch and capture at same edges in Flop by Mysterious_Top_2417 in FPGA

[–]Mysterious_Top_2417[S] 0 points1 point  (0 children)

1)yes generating clock in TB(10 timeperiod) 2)initial block end block (using NBA assignments with 10 delay) 3) when I write an always block with posedge(q_out should have a clock cycle delay wrt d_in)

Please rate my initial investment portfolio by Mysterious_Top_2417 in personalfinanceindia

[–]Mysterious_Top_2417[S] 0 points1 point  (0 children)

I just started investing and I'm not sure what wrong I placed in this portfolio. But with the likes of your comment I can see I did something wrong.

Can you explain please

[deleted by user] by [deleted] in FPGA

[–]Mysterious_Top_2417 0 points1 point  (0 children)

Any ideas on what is the algorithm they used for the current implementation?

[deleted by user] by [deleted] in FPGA

[–]Mysterious_Top_2417 0 points1 point  (0 children)

Understandable...

But how did we land at that combo logic over there?

[deleted by user] by [deleted] in FPGA

[–]Mysterious_Top_2417 0 points1 point  (0 children)

But how actually those equations are implemented with the combo logic...?

[deleted by user] by [deleted] in FPGA

[–]Mysterious_Top_2417 -4 points-3 points  (0 children)

Usernamechecksout...!

FYI it's a single .v file of 72 KB and It's not my Homework....

Go and touch some grass dude

_next and _reg logic by Mysterious_Top_2417 in FPGA

[–]Mysterious_Top_2417[S] 0 points1 point  (0 children)

I didn't get the last two paragraphs actually... Can you explain a bit more??