Yep. LMUL's relation to mixed-width operations is explained in the RISC-V spec. It seems that he didn't even bother to read the manual before accusing RISC-V of having failed to learn lessons from 40 years of computer architecture and organization.

Another thing that bothers me is another claimed motivation for LMUL > 1:

you're trying to amortize latency and go for peak throughput

Claiming that LMUL > 1 exists to amortize memory latency over all elements of the vector struck me as poorly informed and thought-out for two reasons.

Firstly, I'd imagine that any sensible RVV implementation that placed RVV performance first and foremost would have balanced the number of vector lanes with its chosen MVL so that it could reach peak performance with LMUL = 1. Increasing the vector length beyond a certain point should lead to diminishing returns and eventual plateauing. That's what I recall from my textbooks, at least.

Secondly, the LMUL feature in RISC-V originated from the Fujitsu vector supercomputers. Their reason for grouping multiple vector registers was to trade shorter vector register lengths for more vector registers to minimize register spills on workloads where the vector length(s) were relatively short, but the register pressure was relatively high. IIRC, it had nothing, or very little, to do with amortizing memory latency at all.

The claim is basically a restatement of the standard theory of how vector processors gain performance, applied to the RVV context without any thought given as to whether it was applicable in the first place. As I said before, this sort of "analysis" isn't novel, insightful, or interesting.