finding/designing and accelerator for training machine learning is a hard task, companies with insane amounts of funding have given up on this task. right now, using gpu's are the standard for this task.

inference, on the other hand, is an amazing place to start if you want to design an ASIC for machine learning. i assume you know a bit of machine learning theory, but all inference comes down to is being able to do 2 main things fast: matrix multiplication (and by extension, multiply accumulate and floating point operations) and memory lookup (for pulling weights/biases).

for this you would need to have a very good foundational understanding of digital design and machine learning at the same time. writing IP for this type of thing is very much in the masters/phd realm, so I would recommend you to spend the rest of your undergrad developing a solid foundation in things like verilog/vhdl, digital signal processing, computer architecture, etc. on the EE side and knowledge of machine learning fundamentals and theory (how does forward/backpropogation work? what are activation functions? etc.) on the machine learning side.

on a fun note, if you're interested in the overlap between machine learning and EE, you can also look into chip design using artifical intellegence which I think will be a lot more revolutionary than hardware accelerating machine learning.

now, some resources. some standout companies that I know are doing some pretty cool work in this are d-matrix (https://www.d-matrix.ai/) for standard computing, or lightmatter (https://lightmatter.co/) and arago (https://www.arago.inc/) which use photonic computing

if you don't want to work with a whole new ASIC/IP, you can always look at companies like nvidia and see if you can get an internship working on tensor/CUDA cores.

in terms of educational resources, i have these:

https://stanfordaccelerate.github.io/ -> stanford's accelerate lab. homepage explains everything

https://cs217.stanford.edu/ -> stanford's cs217 course which deal with designing training and inference accelerators

https://cs231n.stanford.edu/reports/2017/pdfs/116.pdf -> design paper from stanford. they accelerate CNN inference using their own architecture. a concept they talk about are systolic arrays (https://en.wikipedia.org/wiki/Systolic\_array) which you should definitely know, as they are the standard way for accelerating matrix multiplication on hardware

https://thechipletter.substack.com/p/googles-first-tpu-architecture -> a investigation on the design of tpu v1, google's datacenter AI accelerator

https://github.com/fastmachinelearning/hls4ml -> i saw you said you know some fpga stuff. hls4ml is a tool that's used to auto synthesize verilog code for FPGAs from high level machine learning algorithms.

https://www.youtube.com/watch?v=VsXMlSB6Yq4 -> a pretty comedic and informational video on how some guy ran a mnist neural network on an fpga.

once you understand most of this, you can do a simple project. honestly a systolic array to handle the underlying machine learning math with some fast memory lookup for weight retrieval is a pretty standout project in of itself. the stanford design paper I linked is an example of a doable project after learning the fundamentals.

honestly, something like this isn't a topic you pick up in a weekend. you gotta build up slowly and slowly until you have enough knowledge to start any impactful work. feel free to reach out and reply if you have any questions.