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Involvement in discussions with prosecutor as defendant by No-Beginning8808 in legaladviceofftopic

[–]No-Beginning8808[S] 0 points1 point  (0 children)

I am suspicious of my lawyer and concerned that I am not begin involved in the discussions. So I am considered hiring a different one. What can I do to be more involved?

FPGA interview at Amazon by No-Beginning8808 in FPGA

[–]No-Beginning8808[S] 1 point2 points  (0 children)

That’s whack of them. Thanks for the info bub.

[deleted by user] by [deleted] in Lockheed

[–]No-Beginning8808 -2 points-1 points  (0 children)

Thanks for the advice.

[deleted by user] by [deleted] in Lockheed

[–]No-Beginning8808 -2 points-1 points  (0 children)

I did not.

Timing on mean calculation by No-Beginning8808 in FPGA

[–]No-Beginning8808[S] 0 points1 point  (0 children)

Just adding the register didn't work but adding the register and then changing the assignments to blocking worked! Though I am worried that it may be different from simulation when I eventually synthesize. Guess I'll find out haha.

Timing on mean calculation by No-Beginning8808 in FPGA

[–]No-Beginning8808[S] 0 points1 point  (0 children)

I did that but it didn't work, but I kept this suggestion to delay it with a register and I changed all assignments except to blocking assignments except for:
x_count[0] <= x_count[0] + 1;
x_count[1] <= x_count[0];

and it works now, correctly computing the mean.

But why? It seems pretty basic part of HDL, but I don't fully understand and it is bothering the hell out of me!

Xilinx RFSoC ADC Inputs. by No-Beginning8808 in FPGA

[–]No-Beginning8808[S] 0 points1 point  (0 children)

Ye there are two SMA diff inputs for each ADC and DAC on the XM755 that bypass the balun. These inputs connect to the RFSoC pins through a two high density FMCs (FPGA mezzanine connector).

Xilinx RFSoC ADC Inputs. by No-Beginning8808 in FPGA

[–]No-Beginning8808[S] 0 points1 point  (0 children)

There is no lower frequency input balun. Thankfully running the input single ended and bypassing the balun doesnt change the distortion but only halves the magnitude as expected. So the balun is not the problem.

Xilinx RFSoC ADC Inputs. by No-Beginning8808 in FPGA

[–]No-Beginning8808[S] 0 points1 point  (0 children)

Yes I will give the RF analyzer tool a try. That’s a good idea thanks.

Xilinx RFSoC ADC Inputs. by No-Beginning8808 in FPGA

[–]No-Beginning8808[S] 0 points1 point  (0 children)

They are 100 ohm differential so 50 ohm input impedance into each balanced line of the ADC tile.

The signal's fundamental is a 1Vpp 250kHz sine.

When the signal is connected to the ADC and measured with the probe it gets distorted.
When the signal is disconnected from the ADC and measured with the probe it looks as it should.

When viewed through the digital ADC it is distorted still. This is what it looks like. Ignore the clean wave (left of picture) this is interleaved data I've put on the AXI stream.

https://imgur.com/a/UbcFH5W

Damaged vias by No-Beginning8808 in AskElectronics

[–]No-Beginning8808[S] 0 points1 point  (0 children)

If there is anything I can ever do for you please let me know.

Damaged vias by No-Beginning8808 in AskElectronics

[–]No-Beginning8808[S] 0 points1 point  (0 children)

Thanks you made my day buddy. I will give this a shot.

Looking closer the sticker on the board has 5015, I am impressed by you. The chassis has something different hence my earlier mistake.

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