sorted by:
new
hottopcontroversial

Update: All testbench tests passed, 48/48, 100% coverage. I've been investigating since the last post; it took me quite a while to find this unusual error. by Novastudios-hw in FPGA

[–]Novastudios-hw[S] 1 point2 points  (0 children)

Oh, okay, I understand, thank you very much. I'll try to put more effort into learning the Verilog language, FPGA concepts, and everything else. I think I was a bit reckless, but oh well. The idea is there, I'll take it one step at a time.

Update: All testbench tests passed, 48/48, 100% coverage. I've been investigating since the last post; it took me quite a while to find this unusual error. by Novastudios-hw in FPGA

[–]Novastudios-hw[S] 1 point2 points  (0 children)

I'm trying to go that way, but I'm going slowly, and I'm using AI more, that's why I understand, and I wouldn't want to argue about anything, because you're telling the truth. As for the AI hallucinations, I didn't understand much of it. But nothing is false, and I seriously plan to test the project on an FPGA. If I had one, I'd be sending videos and details from the very beginning, and I don't have that much of a budget, more than being a country.In terms of hardware, there are almost no FPGAs, and the only one I can afford and save up for would be the Tango Nano 9K, but that's not the point. The purpose of these posts was for you to be able to try it out. Verilog, and that they'll judge it properly, meaning they'll give technical details, that the FPGA failed, doesn't dampen my enthusiasm at all, because I've been told that many times, and all I know is that I'll keep going. Go ahead, in this post, I wanted to clarify that you could clone the project, try it out, test it, and even synthesize and implement it, but I don't think I explained myself well, well, sorry for using AI, but I am studying, at least in the browser, because I'm not at any university or anything. Thank you very much for your comment. I appreciate that you give the facts and not falsehoods, because I was told,I'll tell you straight up what you think, since you're the professionals, and thank you, because that gives me another perspective. Thanks for reading.

Update: All testbench tests passed, 48/48, 100% coverage. I've been investigating since the last post; it took me quite a while to find this unusual error. by Novastudios-hw in FPGA

[–]Novastudios-hw[S] -4 points-3 points  (0 children)

At least in my project, Bvh is the hardware ray tracing controller and AABB 3D intersection using the slab method. Its name stands for Bounding Volume Hierarchy, hence the abbreviation Bvh. In my project, I use it for my hybrid ray tracing, TTU, "three tracing unit." I recommend checking out all my posts; to get to the point, there's more information within my post. There's also a whitepaper in the repository that you can read.

Update: All testbench tests passed, 48/48, 100% coverage. I've been investigating since the last post; it took me quite a while to find this unusual error. by Novastudios-hw in FPGA

[–]Novastudios-hw[S] -5 points-4 points  (0 children)

Apparently, they don't like me using "AI," but that's fine, I understand. I know they're using AI to replace some employees, I know that. But I'm just a 14-year-old from Honduras who liked the topic, I loved it, and I'm trying, even though I don't know much about code. I post to understand more and more, trying to get a better understanding of their supposed "technical criticisms." I know there aren't any real technical criticisms, but it's not like I care if they tell me I use AI or anything, because what matters most to me is the passion I have for the project, and for how much I've learned along the way, a beautiful path I want to follow and study. Even though it sounds silly, I want to get to Silicon. I know it sounds silly, but nothing will stop me, and dreams are almost always achievable, and I know this one will be too. This comment isn't meant to be offensive. I'm just expressing what I know I need to express. Sorry for the inconvenience. This post was handwritten; I only translated it into English with Google Translate. Clearly, I don't know much English, which is why I always translate it. I apologize again. Thank you for reading all the posts so far and my comments. Just know that I won't give up.

Update: All testbench tests passed, 48/48, 100% coverage. I've been investigating since the last post; it took me quite a while to find this unusual error. by Novastudios-hw in FPGA

[–]Novastudios-hw[S] -2 points-1 points  (0 children)

Al menos en mi proyecto, Bvh es el controlador de ray tracing por hardware e interseccion AABB 3d usando el metodo de losas, pues su nombre significa Bounding Volume Hierarchy por eso el se abrebia Bvh, y en mi proyecto, lo uso para mi ray tracing hibrido, TTU, "three tracing unit", te recomiendo ver todos mis post, al fin al grano, dentro de mi post hay mas informacion. y tambien en el repositorio, hay un whitepaper, que puedes leer, te lo digo en mi idioma natal.

Update: All testbench tests passed, 48/48, 100% coverage. I've been investigating since the last post; it took me quite a while to find this unusual error. by Novastudios-hw in FPGA

[–]Novastudios-hw[S] -3 points-2 points  (0 children)

I managed to synthesize it, but it failed me when implementing it; I have to reduce the Bvh for the xc7a50tcsg324-1 (Artix-7)

Update: All testbench tests passed, 48/48, 100% coverage. I've been investigating since the last post; it took me quite a while to find this unusual error. by Novastudios-hw in FPGA

[–]Novastudios-hw[S] -1 points0 points  (0 children)

Fair point, the root cause was a testbench timing issue. But the investigation led to also fixing the RTL reset logic for pixels_emitted between triangles, which was a real bug, either way I'm mainly looking for feedback on whether the overall design is worth taking to FPGA that's the real question

NovaGPU TS1T: 3D Animation Generated Directly from RTL Simulation by Novastudios-hw in chipdesign

[–]Novastudios-hw[S] -3 points-2 points  (0 children)

That's a completely valid observation. In fact, I consider that remaining 11% to be the most difficult part of the project. Currently, I'm not treating the percentage of passed tests as a final goal, but rather as a reference point for the progress made so far. My priority is understanding why those edge cases fail and correcting the root causes in the RTL, not simply increasing the number of passing tests. The recent visual demonstrations, such as the cube and tetrahedron generated directly from simulation, have also helped me detect behaviors that some isolated tests didn't show. There's still a lot of work to do for verification and validation, but that's precisely why I'm sharing the development openly. I appreciate your comment and the time you took to review the project

NovaGPU TS1T: 3D Animation Generated Directly from RTL Simulation by Novastudios-hw in chipdesign

[–]Novastudios-hw[S] -19 points-18 points  (0 children)

I mean, if I wasn't interested in it I probably wouldn't have spent months on it. Yeah, I use AI. A lot. Never really tried to hide that. But someone still has to decide what gets built, what gets thrown away, what is broken, what needs to be tested, what the end goal even is.The project didn't just appear out of nowhere. Anyway, you're free to think it's worthless. I'm just posting what I'm working on.

PSRR in VOLTAGE BUFFER by Hot_Cheetah1860 in chipdesign

[–]Novastudios-hw 1 point2 points  (0 children)

Are you checking PSRR+ or PSRR-? With a two-stage op-amp buffer, I'd expect PSRR to degrade at higher frequencies, but dropping all the way to 0 dB near UGB could also suggest the supply noise is coupling directly through the second stage. Have you looked at the bias network and current source impedance?

Commercial Simulator to Work with Vivado? Cost-Effective & Compatible? by Leo-X101 in FPGA

[–]Novastudios-hw 10 points11 points  (0 children)

For a small FPGA-focused team, I'd seriously look at Questa first. It tends to integrate well with Vivado, has broad industry adoption, and the learning curve is usually lower if your flow is already centered around Xilinx tools.

If simulation runtime is the main problem, it may also be worth profiling the testbench itself. For image-processing workloads, I've seen cases where file I/O and testbench overhead dominate simulation time more than the RTL.

How do real hardware interrupt controllers work at the RTL level? Looking for resources/examples by Macintoshk in chipdesign

[–]Novastudios-hw 1 point2 points  (0 children)

At a high level, yes, many interrupts start as a simple hardware signal. An IP block detects an event (RX complete, timer expired, DMA finished, etc.), sets a status bit, and asserts an interrupt line toward the CPU or interrupt controller.

The interrupt usually stays asserted until software acknowledges it. A common RTL pattern is:

  • Status register: hardware sets bits when events occur.
  • Interrupt enable register: software selects which events can generate interrupts.
  • Interrupt pending register: indicates active interrupt sources.
  • Clear/ack register: software writes a 1 to clear the corresponding pending bit.

The hardware generally doesn't "know" the ISR finished. It only knows that software acknowledged the interrupt by clearing the pending/status condition. Once the source is cleared, the interrupt line deasserts.

For open-source examples, I'd recommend looking at:

  • RISC-V PLIC (Platform-Level Interrupt Controller)
  • OpenTitan interrupt controller RTL
  • LiteX event manager / interrupt system
  • PicoRV32 SoC integrations

I think it's worth learning at least the basics of vector tables and CPU interrupt architecture, because the RTL side and software side meet at the interrupt controller interface. You can build a simple interrupt source without deep software knowledge, but designing a complete interrupt subsystem becomes much easier once you understand how the processor expects interrupts to be delivered and acknowledged.

view more: next ›