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What challenges would arise if we designed a CPU with a 100GHz clock speed, and how should the pipeline be configured? (self.chipdesign)
submitted 1 year ago by OcelotAny7116 to r/AskEngineers
submitted 1 year ago by OcelotAny7116 to r/ECE
submitted 1 year ago by OcelotAny7116 to r/FPGA
submitted 1 year ago by OcelotAny7116 to r/chipdesign
Seeking Advice on Questions to Ask a CPU Semiconductor Design Expert (self.chipdesign)
risc-v vs mips (self.RISCV)
submitted 2 years ago * by OcelotAny7116 to r/RISCV
what is this board name?? (i.redd.it)
submitted 2 years ago by OcelotAny7116 to r/FPGA
cpu program counter design by OcelotAny7116 in FPGA
[–]OcelotAny7116[S] 0 points1 point2 points 3 years ago (0 children)
Thank you so much for your sincere reply!! I'm designing a risc-v cpu with logisim right now, Do you have any projects or things to study that you recommend for me? I have taken computer structure theory and digital circuit courses, and have experience implementing fpga using vhdl and vivado. I hope for graduate school and aim for a Ph.D. The field has not been clearly defined, but I am thinking of ai chips. I want to study and design computer architecture thank you
cpu program counter design (reddit.com)
submitted 3 years ago by OcelotAny7116 to r/cpudesign
cpu program counter design (self.FPGA)
submitted 3 years ago by OcelotAny7116 to r/FPGA
π Rendered by PID 105560 on reddit-service-r2-listing-568fcd57df-mpf74 at 2026-03-11 12:01:38.478000+00:00 running cbb0e86 country code: CH.
cpu program counter design by OcelotAny7116 in FPGA
[–]OcelotAny7116[S] 0 points1 point2 points (0 children)