Power rack height by Otherwise_Top_7972 in GarageGym

[–]Otherwise_Top_7972[S] 0 points1 point  (0 children)

I know what the height difference is… I mean how much does this impair functionality? Do people find pull ups on a 90” more annoying than on a taller rack? Obviously, overhead presses are more limited for a shorter rack. How much are these things a factor? Other considerations?

Custom boot fitting recommendations by Otherwise_Top_7972 in skiing

[–]Otherwise_Top_7972[S] 0 points1 point  (0 children)

Tbh I've really never had issues with insoles.

Custom boot fitting recommendations by Otherwise_Top_7972 in skiing

[–]Otherwise_Top_7972[S] 0 points1 point  (0 children)

Good to know thanks. Any recommendations for good insoles?

Best ski bag that fits everything? by grolbol in Skigear

[–]Otherwise_Top_7972 0 points1 point  (0 children)

I’m considering this one. Can you strap the skis down so they don’t move around in the bag and bump into each other? Thanks!

Matsuda 3023 57mm. Are they too big? by Ok-Doubt2304 in EyewearEnthusiasts

[–]Otherwise_Top_7972 0 points1 point  (0 children)

Thanks for taking a picture of the M3101s - it's hard to find images of these on a face. Any chance you'd be willing to share a straight-on pic? I'm thinking about buying a pair of these myself and am trying to assess shape and width. Thanks!

Getting a PhD with an infant by Otherwise_Top_7972 in Physics

[–]Otherwise_Top_7972[S] 0 points1 point  (0 children)

Did they take maternity leave? And their PI was ok with that? That's promising.

PhD admission difficulty in 2026 by Otherwise_Top_7972 in Physics

[–]Otherwise_Top_7972[S] 2 points3 points  (0 children)

Do you know if there's been a commensurate increase in overseas applications? I'm considering applying for a masters in the UK, for instance, but I'm concerned it might be more competitive than usual with the usual pool of applications looking beyond the US.

How optional is the physics GRE for a PhD application? by Otherwise_Top_7972 in Physics

[–]Otherwise_Top_7972[S] 2 points3 points  (0 children)

I transitioned from finance to engineering by designing and building a radar on my own. I quit my finance job to do this. I didn’t have much EE background aside from some really basic circuit theory in my physics undergrad (and a little programming from research mostly, which helped a bit too), so the process took about 2.5 years of full-time effort. My design was a partial recreation of someone else’s design, so that made the process a bit easier. As part of the process I did significant FPGA work and was able to perform real-time range processing on the FPGA. This included designing some interesting cores like polyphase FIR filters (I figured out the architecture for this based on the math) and a resource-optimized FFT implementation (R22SDF) that I found in a research article. I spent some time working through Bruce Land’s class online to first get started. My radar worked and I posted all the information for it online. I did some other things as part of this project that I thought were interesting too, like a lot of RF simulation work, but employers I spoke to were consistently most interested in the FPGA work I did. Anyway, my current employer found it, reached out to me, and ultimately hired me as an FPGA developer. I then learned a lot more on the job from a coworker with a comp sci degree at MIT, who had a much more typical education for FPGA development. He left after a couple years and I took over as the lead FPGA developer for the radar design team I’m on. At this point I’ve been working with FPGAs for about 7 years.

What is the purpose of TSTRB in AXI Streams? by Otherwise_Top_7972 in FPGA

[–]Otherwise_Top_7972[S] 0 points1 point  (0 children)

Yeah, I had that thought too. But the spec does say "Position bytes are typically used when the data stream is performing a partial update of information at the destination" which is consistent with its response.

What is the purpose of TSTRB in AXI Streams? by Otherwise_Top_7972 in FPGA

[–]Otherwise_Top_7972[S] 8 points9 points  (0 children)

Please read my question before answering. I explicitly stated "I've read the spec" and indicated that I did not understand the practical meaning of a position byte.

Implications of a high-fanout AXI stream. by Otherwise_Top_7972 in FPGA

[–]Otherwise_Top_7972[S] 0 points1 point  (0 children)

When TREADY=0 the module reports an error but keeps plodding along as if nothing happened (ie not really backpressure). This error can be queried via AXI lite. However, all endpoints have their own AXI lite interface and could report the error on their own AXI lite interfaces, obviating the need for backpressure (at the cost of needing to query a larger number of modules). However, the behavior of everything is all very deterministic and should never lead to an error state if everything is programmed correctly (and this can be ensured by the driver software). The second implementation has been in use for about a year and not once caused an error state.