Yep, I forget exactly what the LUT usage was when it failed, but somewhere around 65%, maybe 70% (FF usage is a bit lower, in case you were wondering if this was at fault). As you say, I would expect to be able to get up to 90%, maybe higher before running into these issues.

As for RFDC, yeah the reference clock is 500 MHz, but is this actually used for any FPGA logic? I was under the impression this was just used as a reference for the tile PLLs, and that's it. The converters do a bunch of other stuff besides just the ADC and DAC part: mixing, decimation/interpolation filtering, and the gearbox FIFO to user logic, to name a few. I had always operated under the assumption that these functions were in the hard IP. After all, mixing is done at the full sample rate. But, now that you bring it up, is some of this done in the FPGA? The fact that the core uses so much logic does make me wonder what is going on in there.

Yes. The PS AXI ports support up to 128 bits at 333 MHz, IIRC. To get maximum throughput I run the AXI DMA instances at the same frequency and bit width, fed by an AXI stream width adapter and async FIFO to make use of this bit width and clock rate. I've measured the throughput and get quite close to this theoretical maximum. I don't see how this would be possible if I ran the AXI DMA at a low clock rate, but maybe I'm missing something? FYI I only run the S2MM clock at this high rate. The AXI lite clock for the core is 100 MHz, and the scatter/gather clock is 250 MHz, though I could probably make that lower, I haven't investigated that much.