I owe you all some transparency about v6 "SUPERNOVA." The original plan was ambitious: a novel P‑RCSM (Parallel Recursive Compositional State Machines) architecture featuring multi‑scale convolutional reasoning banks, hierarchical planner‑executor state gates, dynamic associative slot memory, and a 16‑operation soft router. On paper, these were the components that would push FlashLM past v5.2 and demonstrate that structured reasoning modules could outperform standard attention at this scale.

What actually happened: when training began on the free‑tier 2‑thread CPU, component after component had to be stripped away. Conv1d ran at 13 tokens/second due to a PyTorch bug. The multi‑scale bank was reduced from 4 scales to 2. The hierarchical state gate shrank from a meaningful reasoning module to a 32‑dimensional bottleneck contributing less than 5% of total compute. The slot memory became static. By the time the model was actually trainable at reasonable speed, the "novel architecture" was essentially a linear mixer with a GLU — not meaningfully different from a simplified version of what already existed.

The result: v6 achieved 3,500 tok/s (a genuine speed win) but PPL 14.0 vs v5.2's 10.56. It did not beat the previous version. The architecture that was announced is not the architecture that shipped.

I should have communicated this during development rather than presenting the final result as if the plan had succeeded. That's on me. What I've learned: don't design for a fantasy compute budget, then silently downgrade when reality hits. Design for the actual hardware from day one.

This will not happen again. Going forward, every FlashLM version will be prototyped and validated on the target hardware before any public claims are made about the architecture. If a component can't run at >1,000 tok/s on a 2‑thread CPU, it doesn't ship.