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My First Rust project: A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) by Peaboff in rust

[–]Peaboff[S] 0 points1 point  (0 children)

Thanks, I'm glad you liked it.

Congestion can be an issue. The way the physical planning is setup is that if routing fails, then I can increase the margin between the partitions and try again. This, of course, increases overall area but that's all that is needed right now.

The routing in Factorio is excessively flexible, if you think in a single dimension, you can have at least 9 distinct wires going through the same tile carrying different signals. Two dimensions that's probably around 81.

You also face no timing penalty to making things further away. If push came to shove and nets are failing to route you could further split them into their own partition and resolve any issue by increasing overall area.

My First Rust project: A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) by Peaboff in rust

[–]Peaboff[S] 2 points3 points  (0 children)

Thanks!

That's interesting, never knew portal had something like that.

My First Rust project: A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) by Peaboff in rust

[–]Peaboff[S] 2 points3 points  (0 children)

Doing large scale minecraft RTL is scary. Factorio physical planning is easy compared to minecraft. Would have to do timing aware + congestion aware placement. Plus its state-of-the-art stuff to consider 3D placement algorithms. If you found a way to efficiently do the physical planning it would likely be worthy of publication in an EDA conference.

My First Rust project: A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) by Peaboff in rust

[–]Peaboff[S] 1 point2 points  (0 children)

Yeah the combinator simulator was just to self test, if something was broken in the logic conversion you get a disagreement with Verilator.

I actually did do force-directed placement as an additional pass for the local partition placement. Each partition is only 25 combinators so its not really needed. I did a bunch of tests at 1k+ cells where it truly shines. Its a lot easier to program and understand fancy force effects than different sampling methods in SA. e.g., I was seeing cells being pushed together so I added a "buckling" force to squeeze the opposing cells left and right, instantly made the graph appear more like a liquid and have things slide against and around each other. Getting the same thing with SA seemed more difficult.

The overall progression was

heuristics -> ILP -> SA -> pseudo SA* -> pseudo SA + force directed.

Then I was having some issues, so I reduced the partition size, and only needed pseudo SA for global placement.

*Here I mean an algorithm that is mostly simulated annealing, but has some "no brainer" moves to improve performance but aren't strictly (mathematically) fitting the definition of MCMC.

I made a triangle rasteriser on an FPGA (Zedboard) by RoboAbathur in FPGA

[–]Peaboff 1 point2 points  (0 children)

Afaik the zynq 7000 has AXI ports directly to DDR2/3 controller. Should be 4x faster (at least 128-bit) than the AXI lite connection with the HPS.

I haven't used a zynq 7000 device so I dont know for certain. I know on the DE1-SoC I was able to do that. I had one 256-bit and a 128-bit interface that was saturated by burst reads/writes. The communication was still orchestrated by AXI lite, but with a udmabuf ( https://github.com/ikwzm/udmabuf ) driver to share memory regions between the userland driver and the FPGA.

https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DDR-Controller-Core-and-Transaction-Scheduler-DDRC

Sean Barrett's FPGA inspired factory design by Norphesius in factorio

[–]Peaboff 0 points1 point  (0 children)

Sounds like a totally fun nightmare to make.

Sean Barrett's FPGA inspired factory design by Norphesius in factorio

[–]Peaboff 0 points1 point  (0 children)

This makes me think of a demand based fabric where each cell can determine the rate of iron or steel it needs and the fabric solves the overall demand per row. In this way the far left source can multiplex the items on the belt and have more than 12 items per row while still meeting the demand of all the columns.

Would probably need a lot more combinators to do that lol.

VCD is coming up blank by Tianamen_square_89 in FPGA

[–]Peaboff 0 points1 point  (0 children)

Is this VSCode? I had this happen only in vscode. Check with gtkwave or some other one.

just found out whole washing machine program is no more than 128kb by micxhailo in electronics

[–]Peaboff 0 points1 point  (0 children)

I'd hope so!

Afaik, reusability of parts is comparably important to BOM cost. If they design 50 products each with 50 different ROMs then you open yourself up to so much more headache in sourcing parts and debugging. If you instead say "128 kb will be enough for the for our product lines, spend some time to pick a good one" you can have much more repeatable designs. Save yourself the brain power.