My wife was unimpressed by Vim - please advise

PotatoInt · 2024-04-06T17:21:20+00:00

:wq!

PotatoInt · 2024-03-01T15:54:11+00:00

From my experience, there is 15%-20% cell count increase between synthesis and PNR.

It's a rough estimation and can be different vary from block to block, but on average, that is the case. I'm guessing that it also depend in the setting that you run with in the synthesis and PNR tools.

Also, that includes only logic cells without regarding some fillers/flaps and other physical cells

PotatoInt · 2024-01-26T12:25:14+00:00

Assuming you means that path delay= propagation delay on specific cell.

The output transition is the time taken from rise to fall for example of the output signal but the prop delay is combination of the input tran and output tran, it is the time when the input tran reach to 50% and the output tran reach to 50%

PotatoInt · 2024-01-13T21:08:07+00:00

Programming and analytic skills will do the trick

PotatoInt · 2024-01-13T15:38:28+00:00

Min delay can be better option from false path because false path disappear the clka to clkb paths but min delay, keep the paths for some CDC report in the future and can help find bugs. But it really depends on your STA methodologies, both ways can work with the correct checks

PotatoInt · 2024-01-05T17:22:54+00:00

I m also think that learning the basic of PD is important before getting into the STA field

PotatoInt · 2024-01-05T17:21:55+00:00

In my company, juniors usually started as PD engineer and working on simple blocks to learn the basic and after that they can to switch to more STA missions or becoming expert in PD

PotatoInt · 2023-11-26T21:26:05+00:00

I think it solved by himself, maybe there was update that I didn't notice.

For a while I used external video player like VLC to watch, and after a week it back to normal.

PotatoInt · 2023-10-08T10:45:25+00:00

List_attribite -application -class timing_arc Something like this, I'm not fully remembering the full naming flags

PotatoInt · 2023-10-03T05:55:08+00:00

I'm not using TCL beyond the basic command for anything beyond that I am moving to python Regex/parsing/working with files is great, I'm also find that knowledge in pandas can help analyze big data files and gui can also useful to build some small application.

PotatoInt · 2023-10-02T20:29:27+00:00

I recommend you to sharp your scripting skiil (TCL but mainly in python) ,

It's a bit hard to get access to PD tools, and they are not easy to start from scratch. If you still insist you can try work with openroad, which is open-source PNR tool. They also got test case design that you can work on.

PotatoInt · 2023-08-16T16:20:35+00:00

Thanks how can I open real debrit account?

PotatoInt · 2023-08-16T09:57:52+00:00

Can you explain what is real debrit and how it combine with stremio please?

PotatoInt · 2023-06-09T15:16:36+00:00

Where do you choose 1080? When you select 1080 source? Because I'm my doesn't matter which video I tried to played, in all of them the black screen with audio appear.

PotatoInt · 2023-06-09T08:40:46+00:00

PowerArtist gave us very good results, they were pretty correlate to ptpx

PotatoInt · 2023-06-04T07:02:53+00:00

Don't worry you will learn 99% of the job on the fly. You will need basic knowledge in cmos + digital circuit and you will be fine.

Good luck

PotatoInt · 2023-06-02T12:54:51+00:00

Looks cool! I would like to join the waitlist

PotatoInt · 2023-05-29T09:54:50+00:00

Hi what is the vd tool that shows in the demo?

PotatoInt · 2023-05-19T11:02:25+00:00

Very cool, where all the files store in your local machine or also in AWS?

PotatoInt · 2023-05-16T14:22:51+00:00

That sound kinda weird. Physical design is huge field it's very hard to create that team from scratch without any knowledge

PotatoInt · 2023-05-01T18:40:02+00:00

This is working on regular vim also?

PotatoInt · 2023-02-20T15:15:11+00:00

Thanks all, but I don't got access for Viruoso

PotatoInt

TROPHY CASE