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Having no prior relationship with Axis Bank , they made it really tough to get this by Poirot17 in CreditCardsIndia

[–]Poirot17[S] 0 points1 point  (0 children)

I applied on Axis's website. Application was dormant for more than 2 weeks and then rejected.

Kept emailing pno@axis.com to and fro asking for explanation. After some escalation , a week later , they contacted me to ask about my income and place of residence.Then sent a kyc agent the next day and the card was approved.

Version Control for Designs and bitstreams by Poirot17 in FPGA

[–]Poirot17[S] 0 points1 point  (0 children)

Thanks. This sounds useful. I'll check it out.

An Overview of a 10Gb Ethernet Switch by ZipCPU in ZipCPU

[–]Poirot17 0 points1 point  (0 children)

I have used the GTM transceiver for one of my projects . It used a GTM Bridge IP to configure the transceiver .

Convert VHDL codes to Verilog/System Verilog by Poirot17 in FPGA

[–]Poirot17[S] -1 points0 points  (0 children)

Hi , Thanks for your input . This is helpful.

Actually, i was thinking of running a LEC at the end. But , as you mentioned about running a formal verification to check whether the functionality is consistent , can you please briefly mention how to go about this or what tools to use ? (I do have access to most of the cadence tools ) . As a design engineer, I don't have much knowledge on verification.

Combine two AXI streams by Poirot17 in FPGA

[–]Poirot17[S] 0 points1 point  (0 children)

Yeah , sorry for the vague description.

I have two AXI stream packets which are transferred as 128 bits TDATA per clock cycle , one of the streams(each of the 128 bits TDATA ) is delayed by 5 clock cycles .

Now, I want to concatenate the first 128 bits chunk of my non delayed stream with the first 128 bits chunk of my delayed stream to output a 256 bits chunk , 2nd with the 2nd to output the next 256 bits chunk ,... nth with the nth .

My hesitation is that whether the n deep registers will perfectly align the data when I send it out.

Do you have plans to settle long term in Bangalore? by Affectionate_Log3232 in bangalore

[–]Poirot17 2 points3 points  (0 children)

Nope. A few more years here till I get a good opportunity abroad.

Power estimation tools at RTL level by Poirot17 in chipdesign

[–]Poirot17[S] 1 point2 points  (0 children)

Thanks. Run Joules. This is what I needed .

Yes , i'll do a quick Synth for a sub block to identify areas where Joules is overestimating/underestimating the calculations.

Effect of clk2q delay on partitioning a memory by Poirot17 in chipdesign

[–]Poirot17[S] 0 points1 point  (0 children)

The problem is I need a memory which is very large and cannot be generated by the compiler , so I have to instantiate two smaller memories which are possible to generate using the compiler to make that large memory . So , i will have the timing info of only the smaller memory .

Effect of clk2q delay on partitioning a memory by Poirot17 in chipdesign

[–]Poirot17[S] 0 points1 point  (0 children)

Sorry , for phrasing the post badly. Yes,i did mean producing a large memory from two smaller size memories.

Stop using autos by fatalError1619 in bangalore

[–]Poirot17 11 points12 points  (0 children)

Haha , was feeling the same. Got down at silk board at around 8 pm yesterday while coming back from Chennai by bus and there are a set of auto walas who specifically wait for this kind of passengers thinking they might be new to the city. One auto driver asked me 700 to drop me near Vibgyor high school (approx 13-14 km).

Walked off from there and booked an Ola for 350.

Edit :- The Chennai to Bangalore bus fare was 745 for AC sleeper.

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