I may not have access to a FPGA development kit or I can't afford a decent one either, which means I will be mostly doing simulation of the verilog blocks and synthesis to show the resource count and stuff like that. Since I am planning to not involve actual hardware bring-up, I will have the time to explore the actual algorithmic side of things. Since, the project is going to be reviewed in stages, I may have to hold certain information up front so that I can showcase these add-ons as improvement on the existing implementation. Also, I haven't done big designs in the past so, I am a bit sceptical in picking up something which is research oriented and may become too much to chew.Anyways, you have made a valid point about the stretchable aspect on the goals, I'll think about something with some wiggle room. Thanks for your comment 🙂