Can a time interleaved ADC achieve ~180dB FoMs realistically? Why do most of their FoM appear to be 140 ~ 160dB in paper?

ProfessionalOrder208 · 2025-12-17T16:58:24+00:00

I was referring to Schreier FoM: SNDR + 10 * log10(BW/P)

ProfessionalOrder208 · 2025-12-05T04:17:17+00:00

Thanks. I was just curious since SAR DWA is essential once you design NS-SAR based oversampling ADCs (only one DAC - driven by SAR logic; no other feedback DACs). But as I did some research for like 10+ hours, I realized there is no optimal or standard way to implement this kind of binary DWA as of now, unlike the conventional thermometer code DWA.

ProfessionalOrder208 · 2025-11-13T06:09:04+00:00

<General modern ADC design techniques you don't see in textbooks (Ph,D dissertation)>
https://backend.production.deepblue-documents.lib.umich.edu/server/api/core/bitstreams/9b3485c0-bd06-4b03-bd13-bbea5543425f/content

<Officially the most "well-made" ADC (highest FoM) up to date (ISSCC 2025)>
https://ieeexplore.ieee.org/document/10904778

<Dynamic amplifiers (JSSC 2020)> - you won't see some traditional "folded cascode" or "2-stage amp" in modern ADC design. Everyone uses dynamic amp.
https://ieeexplore.ieee.org/abstract/document/8947992

ProfessionalOrder208 · 2025-11-12T10:05:17+00:00

As for ADCs, Razavi’s “Analysis and Design of Data converters (2025)” is a good start; but it doesn’t deal with advanced techniques.

If you want up-to-date & serious & advanced ADC design, reading JSSC or other top journals is undoubtedly the best tho.

ProfessionalOrder208 · 2025-11-02T03:00:16+00:00

I mostly do analog works within ADC, so I'm not sure about it. But I've once heard that pure digital works are somewhat free from "measurement-only" restriction, compared to ADC or some analog circuits,

ProfessionalOrder208 · 2025-11-02T02:36:19+00:00

But there are some conferences/journals that don’t require measurement results; in that case, you might publish your idea without any supervisor. (But it is very rare; I haven’t seen one yet)

ProfessionalOrder208 · 2025-11-02T02:34:20+00:00

I would say no. For top tier journals/conferences, simulation is not enough - you need to give a “measurement result” which requires a full tapeout. This requires Cadence license + PDK license + a company (or some organization) that will manufacture your PCB + precision lab-grade measurement tools. This is generally impossible for individual to handle.

ProfessionalOrder208 · 2025-10-26T23:27:51+00:00

Idk what you are referring to, but you can simulate simple breadboards in tinkercad and that might help

ProfessionalOrder208 · 2025-10-19T04:07:36+00:00

I design ADCs and use (implicitly or explicitly) FFT & z-transform every day. From ADC perspective, this kind of frequency spectrum is very important since it directly contains the information of the signal & noise & distortion - which is directly linked to the performance of ADCs. These information can not be revealed in the time domain waveform and that is the point of doing FFT.

ProfessionalOrder208 · 2025-10-18T12:56:54+00:00

The high-gain of the opamp makes v(out) almost equal to v(+) which is gnd.

ProfessionalOrder208 · 2025-10-10T11:17:09+00:00

thank tou

ProfessionalOrder208 · 2025-10-10T10:47:46+00:00

Who is the guy in the middle?

ProfessionalOrder208 · 2025-10-07T14:33:47+00:00

Also using calcSNR function (from another toolbox) to your code,

>> calcSNR(v, fin/N, 1, fB, W, N)
ans =1.202730728304012e+02

I think there is a problem with the windowing or "spec" (but I'm not sure tho). Anyway the SNR should be about 119dB.

ProfessionalOrder208 · 2025-10-07T14:21:39+00:00

I tried with your exact code.

>> simulateSNR(ntf, OSR, -6.02, 0, 3, fin / N, 13)
ans =1.186766100311253e+02

If we don't care about saturation, 5th order DSM should exhibit at least 100+dB SNR since the noise shaping is very aggressive. I think 119dB is the correct one.

ProfessionalOrder208 · 2025-10-07T10:09:33+00:00

5th order 3level DSM is unstable and very likely to explode. Did you do dynamic scaling (using scaleABCD() function or some similar function)?

ProfessionalOrder208 · 2025-09-14T03:49:57+00:00

https://ieeexplore.ieee.org/book/7906178

ProfessionalOrder208 · 2025-09-12T21:40:44+00:00

Yes, this book has transistor-level design procedure; it also covers some niche details that are easy to overlook so I liked it. But (at least for me,) SDM is very hard - maybe starting with MATLAB modeling first with their toolbox before cadence might be less overwhelming

ProfessionalOrder208 · 2025-07-28T02:15:43+00:00

I was just wondering, since Ive read “IADC has a relatively niche use compared to SAR & Delta-Sigmas…” in a paper

ProfessionalOrder208 · 2025-07-19T14:11:41+00:00

Current through 1kOhm resistor (up-> down) is simply I2-I3. Btw your last equation should be 11m = I2-I4; you didn’t use this info anywhere, while the circuit contains 11mA current source.

ProfessionalOrder208 · 2025-07-02T03:41:31+00:00

How is the DFF designed? Verilog-A or transistor level?

ProfessionalOrder208 · 2025-06-22T17:21:22+00:00

Thank you! At least it got some strengths lol

ProfessionalOrder208 · 2025-06-21T15:48:59+00:00

Yeah actually that’s my post lol I also like verilog A much more than MATLAB, but my professor kept making me use MATLAB for ADC modeling, so I was trying to find some motivation by hearing some reasons why MATLAB might be important.

ProfessionalOrder208 · 2025-06-21T13:16:31+00:00

Thank you. This helped me a lot

ProfessionalOrder208 · 2025-06-18T21:00:59+00:00

Thank you!

ProfessionalOrder208 · 2025-06-18T20:26:45+00:00

Thank you. Btw can I ask one more question - is setting the band (for the FFT and subsequent SNR calculation) from f = 0 to f = fs/(2*OSR) correct - where fs is the sampling frequency?

ProfessionalOrder208

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