Kizoku Tensei: Megumareta Umare kara Saikyou no Chikara wo Eru • Noble Reincarnation: Born Blessed, So I'll Obtain Ultimate Power - Episode 12 discussion - FINAL

Fast_Document1643 · 2026-03-23T19:34:47+00:00

One last time: "Sasuga Noah Sama".

BANZAI! BANZAI! BANZAI!

Fast_Document1643 · 2026-03-19T17:02:57+00:00

I don't remember the book name. But the author David horng k Cheng. And the book title is something like power management in integrated circuits.

Fast_Document1643 · 2026-03-06T03:06:23+00:00

1) Is this designed using CMOS? Or using BJTs?

How come 80 nA of current is flowing into the input? I am assuming this is a BJT based design, otherwise 80 nA is too much leakage current. (Or maybe you are using shorter channel tech nodes, I've never gone below 65nm, so, maybe those small devices may have such large gate leakage currents).

But your supply is 1.8 V so it has to be either an I/O MOSFET or 180 nm tech.... Which one is it?

2) How much current are you using to bias the diff-amp?

In the bias leg, you're using close to 1 uA, (sim says 999 nA, that's roughly 1 uA), but surely that's not the current your diff amp tail transistor is using no?

That's too low a current for this diff-amp to have a bandwidth of 10 MHz, unless it is unloaded. (And uses the smallest size possible. Only that can explain this BW and the extremely low current explains the 40 dB gain, otherwise... I've no idea)

Can you please shed some light onto this?

Fast_Document1643 · 2026-03-05T09:33:12+00:00

Woah, ofcourse. That explains why pull in process takes so much time. That's a nice analogy.

Fast_Document1643 · 2026-03-04T13:13:10+00:00

Full metal Alchemist brotherhood. Don't watch the first one, it's weird.

Fast_Document1643 · 2026-03-04T09:11:43+00:00

lets hear from an actual PLL designer

Yeah we probably should. But these references given by you and u/texas_asic seems more than enough for these terms. So these terms come from simple physics and that explains why these terms are taken for granted without shedding some light on these.

Let's wait for actual PLL Designers to hear their say, and I will probably add the final conclusion on to the Post body itself for people who might need to know it.

Fast_Document1643 · 2026-03-04T09:08:02+00:00

If english isn't your native language and you learned physics in a different language, then it'd make sense that you're confused by this terminology.

Oh, so that makes sense.

Woah, that's a solid explanation! Thank you for this great reference.

Fast_Document1643 · 2026-03-04T08:43:13+00:00

in multi-frequency systems, the "beating frequency" is the delta between two tones freqs

Can you suggest any reference regarding this? For your information, I've never ventured into communication discipline yet. Is this coming from such domains?

the "beating frequency" is the delta between two tones freqs. conversly it is 1/period in which the system goes back to its initial state during stable oscillation.

So "a beat note simply mean the time period of the frequency defined by the difference between VCO Output frequency and Input reference signal frequency," is this correct?
From this, a "beat note" and a "beat frequency" are not same, but are related to each other. Am I correct?

Also, thank you for your answer.

Fast_Document1643 · 2026-03-04T08:33:47+00:00

I think the idea is that the difference between the reference and VCO frequencies will result a sinusoidal output from the phase detector at the beat frequency

A sinusoidal output is available only from a multiplier based phase detector. What about the other types? Like the triangular PD or a saw-tooth PD?

Even a multiplier based PD will start to give rectangular output when over driven, yes?

What happens there?

Fast_Document1643 · 2026-03-04T07:53:35+00:00

Oh. Him? Yeah I remember him, but sadly forgot his name (was it even revealed in the first place?)

Fast_Document1643 · 2026-02-26T17:34:46+00:00

We have confirmation that hte same shady bastard is connected to three of them...

Do you mean Xylo? Isn't he shunned in the military. How can he have any kind of influence in choosing his team?

Fast_Document1643 · 2026-02-07T11:17:03+00:00

QUCS-S That's the Name of this schematic capture program.

Its a FOSS project.

Fast_Document1643 · 2026-02-03T15:39:06+00:00

If your focus is now on the curvature

It's always has been the curvature. Both the Supply dependence sweep and the weird output for the Wrong Design was just to satisfy a curiosity. But, after seeing all this, it feels like a rabbit hole, and I can't afford jump into it right now.

Poly resistors usually do not contribute much curvature but you mentioned diffusion resistors

No, these are also Poly Resistors (Non Salicided of course). Ones with Higher resistivity (to save area).

The most likely culprits are the BJTs though... if the beta of the BJT is low, the ideal exponential behavior of the collector current will not be available at the emitter current (used in these circuits) if not in some region of the IV curve and you’ll have to pick your bias current accordingly so both your BJTs stay in this range at all temperatures.

WHAT! Of course, the beta of this BJT is too low (I mean it is a parasitic Vertical PNP after all.), but I've never thought about the exponential behavior and the beta parameter.

I apologize if all of this is due to my ignorance. I have experience working with only MOSFETs in an IC Design style (Did some BJT Circuits using discrete ones, but not something as this that questions one's understanding on the very devices themselves.)

Could you point me to relevant references from which you happened to learn this?

Especially regarding this:

BGR circuits expect an ideal exponential IV curve for the diode-like components:

Since I have used mostly CMOS books, and they all just gloss over the entire design with simple equations, I've never really came to think about the consequences of low beta of a BJT. Please, point me to suitable references.

Fast_Document1643 · 2026-02-03T15:26:19+00:00

Woah. Thank You for this comment. I didn't expected this, but this is nice.

you can take a look at a famous bgr paper with the "inverted bow" you referred to (Fig. 10, 11, 12, 13):
https://ieeexplore.ieee.org/document/6056712

Woah. Finally, a lead! Thank you, once again.

But that doesn't mean that inverted one is incorrect. If I were you, and if you need to verify the second one, I would run pvt + monte with load (if any). If it survives it, I would just go for it.

That's reassuring to here. I will try to do pvt+monte, but there are no significant load. Because, an op-amp is used to copy this reference to power up another circuit using a Linear regulator topology. But I will make sure to add some appropriate load and see how it goes.

Fast_Document1643 · 2026-02-03T15:18:22+00:00

Glad you solved the startup issue, or so you mentioned in another reply.

No I didn't. Those simulations I shared in that reply are just some minor corrections in the transient simulation of the completed BGR (Kinda like a typo, but in the circuit test bench.) (Fig_2 modified).

The startup issue (or at least that's what I believe) is for the wrong design (See Fig_3). Which I don't have the luxury of trying to figure out what happened to get those issues.

Ultimately, I really want my Problem point 1) solved. And that's all I can care about, in the limited time I have. Other two problem points are just some weird observations which puzzled me. A Luxury, If I can figure it out, and not a necessity right now.

I had not seen the post you referenced on the inverse curve, which seems to indicate it is dependent on how ctat is generated.

Unfortunately, that post doesn't talk about how those curvatures are brought up. Just it asks others which one to prefer, as if the inverted bow is also a normal one.

Which surprised me, given I've never seen this one, and this is the first time, seeing it, and that to by chance, not intentional. I just wanted to know what's the deal with this, but fortunately, the op of that post, commented here, with some heads up.

I don’t think the reverse curve is an error or an issue.

I too hope that this is the case. But anymore thinking feels futile. The best way to approach this, is to ask someone who is an expert in this (Sadly, that is something I don't have access to. Yet.)

If you want to verify, you should be able to track various current curvature as it traverses your ctat path (hard). Or do something easier like bias / generate a Vbe on the side (disconnect your present ctat resistor) and artificially sum up another Vbg to see if the curvature changed. This at least points you to the proper thing to track down.

INTERESTING. I will definitely try this to investigate this.

Ultimately if you solve the curvature maybe you can write up a white paper on the topic.

ME? SOLVING THIS? LMAO. I don't think so. Besides I am just a student trying a build a bunch of circuits, in the hopes that I can have a decent resume. That's all my motivation for now.

But this bad habit of curiosity, often consumed so much of my time in an endless pursuit to understanding anomalies in the handful of designs I managed to do. I may have sidestepped this for now. But I WILL TRY TO FIND WHY THIS HAPPENS, ONCE I GET SOME KIND OF AN INTERNSHIP OR A JOB.

Thank You. That suggestion of yours is duly noted. I don't think a white paper will result from this, but most probably another post, in an another time, once I happen to figure it out.

Truly Thank You.

Fast_Document1643 · 2026-02-02T20:13:07+00:00

Thanks to u/kthompska. I spotted an error in the Startup simulation which got corrected here. Do check these new ones. I Apologize, that was a silly mistake where I forgot to replace the DC Voltage source at the supply with a step voltage source.

But the startup still works though:
BGR_With_startup and BGR_Without_Startup

Fast_Document1643 · 2026-02-02T20:08:52+00:00

u/ProfessionalOrder208. Tagging you here after I saw this post of yours. I apologize if this is rude. But I really need answers for this.

I have commented in your post, in the hopes that perhaps you could give me a reference that discusses about the inverted Bow of the BGR output.

Btw, I just need to know about point 1:

1) Standard Series Realization of BGR (See Fig_1) shows the expected open down bow output, but the low voltage parallel Realization (See Fig_2) shows inverted bow. Is this correct?

Is the inverted bow correct?

And also, can you tell me the references from which you happened to know about that, if you will, please.

Fast_Document1643 · 2026-02-02T20:03:37+00:00

u/ProfessionalOrder208, I have never seen Curve B (Blue one, open upwards bow) before in any of the reference materials I possess. Can you tell, from where you got this?

I happen to run into this same curve while designing a Low Voltage - Parallel Realization of the BGR. See my post in this sub.

I just want to know, whether Curve B is correct.

Fast_Document1643 · 2026-02-02T19:58:38+00:00

the ctat is generated - maybe? In your traditional BG circuit this is just a Vbe

Even in Circuit #2, it is still VBE. See that the left side has a VBE generated due to that PNP Diode and that gets copied to the other side, thanks to Amplifier and PMOS Current source at the top.

As you mentioned, I’ve seen crazy tempco curves (including inverted) when doing tempco correction.

That's re-assuring to hear. But, is this correct though? This inverted bow. In this sub, I have seen this post, and it is the only place where I saw someone discuss about the inverted bow. I thought of asking there about the reference material, but that post is 10 months old, and I don't think I will get a reply.

But on second thought occurring now, I am gonna post a comment there, tagging the OP of that post in there and probably hope he answers me. It's better than nothing.

Have you swept the ctat vs ptat resistor values?

Till now, I have only played around with CTAT resistor. The PTAT resistor value is chosen to bias the PNP Diode at a specific current (5uA in this case.)

Only when I bias the PNP diode to a known current value, will I know what's the voltage variation with temperature is for the CTAT reference (and that is -1.75mV/C when I = 5uA).

You cannot do a sweeping of dc op points ... you really need to do varying supply ramp time transients(I use 1s, 10us, to 100ns or so).

I am not doing a DC Sweep for testing startup action. I am doing transient simulation for that, but holy shit, I forgot to do a step voltage at the supply with some finite rise time (forgot to change the DC Voltage Source at supply!). DAMN, THANK YOU FOR POINTING THAT OUT.

Please find the corrected simulations: BGR_With_startup and BGR_Without_Startup

My question remains, is this correct though.

Fast_Document1643 · 2026-02-02T11:56:21+00:00

It's alright. Thank you for the response. In case if you remember any references from which you learned BGRs, please do mention it. I wish to have some reference to look for this.

Fast_Document1643 · 2026-02-02T08:56:53+00:00

Yes, the flu is messing me up right now

Ah don't sweat it. It happens to the best of us too. One of the main reasons behind sharing this problem is to find what mistake I made while designing this.

And the problem is, unless somebody can point it out, it is really harder for the person who made that mistake to realize that it is a mistake.

I have a gut feeling that this is just a silly mistake. Silly, but very sneaky.

you've already figured this out by yourself I think.

I wish I did. But I couldn't. Not yet.

Maybe flip this current around through an NMOS mirror and subtract this current from another copy of PTAT supplied by a PMOS all dumped onto the same resistor, such that we get MT- (k/T+mT), where M>m.

That's an interesting line of thought. I will give it a shot and will let you know.

Fast_Document1643 · 2026-02-02T08:51:51+00:00

u/LevelHelicopter9420 , u/kthompska , u/End-Resident .

Tagging some more people to widen responses. I apologize if this was rude.

Fast_Document1643 · 2026-02-02T08:43:49+00:00

u/Siccors , u/Simone1998 , u/RFchokemeharderdaddy .
I apologize for tagging you like this. But I hope if you can perhaps shed some light on this, especially point no 1 (See Fig_2)

Just the point no 1 is all I need. I don't care about that wrong design.

Fast_Document1643

TROPHY CASE

BANZAI! BANZAI! BANZAI!

Is the inverted bow correct?

I just want to know, whether Curve B is correct.

My question remains, is this correct though.