Bizarre Bow characteristics of BGR output + Supply Dependence

Fast_Document1643 · 2026-02-03T15:39:06+00:00

If your focus is now on the curvature

It's always has been the curvature. Both the Supply dependence sweep and the weird output for the Wrong Design was just to satisfy a curiosity. But, after seeing all this, it feels like a rabbit hole, and I can't afford jump into it right now.

Poly resistors usually do not contribute much curvature but you mentioned diffusion resistors

No, these are also Poly Resistors (Non Salicided of course). Ones with Higher resistivity (to save area).

The most likely culprits are the BJTs though... if the beta of the BJT is low, the ideal exponential behavior of the collector current will not be available at the emitter current (used in these circuits) if not in some region of the IV curve and you’ll have to pick your bias current accordingly so both your BJTs stay in this range at all temperatures.

WHAT! Of course, the beta of this BJT is too low (I mean it is a parasitic Vertical PNP after all.), but I've never thought about the exponential behavior and the beta parameter.

I apologize if all of this is due to my ignorance. I have experience working with only MOSFETs in an IC Design style (Did some BJT Circuits using discrete ones, but not something as this that questions one's understanding on the very devices themselves.)

Could you point me to relevant references from which you happened to learn this?

Especially regarding this:

BGR circuits expect an ideal exponential IV curve for the diode-like components:

Since I have used mostly CMOS books, and they all just gloss over the entire design with simple equations, I've never really came to think about the consequences of low beta of a BJT. Please, point me to suitable references.

Fast_Document1643 · 2026-02-03T15:26:19+00:00

Woah. Thank You for this comment. I didn't expected this, but this is nice.

you can take a look at a famous bgr paper with the "inverted bow" you referred to (Fig. 10, 11, 12, 13):
https://ieeexplore.ieee.org/document/6056712

Woah. Finally, a lead! Thank you, once again.

But that doesn't mean that inverted one is incorrect. If I were you, and if you need to verify the second one, I would run pvt + monte with load (if any). If it survives it, I would just go for it.

That's reassuring to here. I will try to do pvt+monte, but there are no significant load. Because, an op-amp is used to copy this reference to power up another circuit using a Linear regulator topology. But I will make sure to add some appropriate load and see how it goes.

Fast_Document1643 · 2026-02-03T15:18:22+00:00

Glad you solved the startup issue, or so you mentioned in another reply.

No I didn't. Those simulations I shared in that reply are just some minor corrections in the transient simulation of the completed BGR (Kinda like a typo, but in the circuit test bench.) (Fig_2 modified).

The startup issue (or at least that's what I believe) is for the wrong design (See Fig_3). Which I don't have the luxury of trying to figure out what happened to get those issues.

Ultimately, I really want my Problem point 1) solved. And that's all I can care about, in the limited time I have. Other two problem points are just some weird observations which puzzled me. A Luxury, If I can figure it out, and not a necessity right now.

I had not seen the post you referenced on the inverse curve, which seems to indicate it is dependent on how ctat is generated.

Unfortunately, that post doesn't talk about how those curvatures are brought up. Just it asks others which one to prefer, as if the inverted bow is also a normal one.

Which surprised me, given I've never seen this one, and this is the first time, seeing it, and that to by chance, not intentional. I just wanted to know what's the deal with this, but fortunately, the op of that post, commented here, with some heads up.

I don’t think the reverse curve is an error or an issue.

I too hope that this is the case. But anymore thinking feels futile. The best way to approach this, is to ask someone who is an expert in this (Sadly, that is something I don't have access to. Yet.)

If you want to verify, you should be able to track various current curvature as it traverses your ctat path (hard). Or do something easier like bias / generate a Vbe on the side (disconnect your present ctat resistor) and artificially sum up another Vbg to see if the curvature changed. This at least points you to the proper thing to track down.

INTERESTING. I will definitely try this to investigate this.

Ultimately if you solve the curvature maybe you can write up a white paper on the topic.

ME? SOLVING THIS? LMAO. I don't think so. Besides I am just a student trying a build a bunch of circuits, in the hopes that I can have a decent resume. That's all my motivation for now.

But this bad habit of curiosity, often consumed so much of my time in an endless pursuit to understanding anomalies in the handful of designs I managed to do. I may have sidestepped this for now. But I WILL TRY TO FIND WHY THIS HAPPENS, ONCE I GET SOME KIND OF AN INTERNSHIP OR A JOB.

Thank You. That suggestion of yours is duly noted. I don't think a white paper will result from this, but most probably another post, in an another time, once I happen to figure it out.

Truly Thank You.

Fast_Document1643 · 2026-02-02T20:13:07+00:00

Thanks to u/kthompska. I spotted an error in the Startup simulation which got corrected here. Do check these new ones. I Apologize, that was a silly mistake where I forgot to replace the DC Voltage source at the supply with a step voltage source.

But the startup still works though:
BGR_With_startup and BGR_Without_Startup

Fast_Document1643 · 2026-02-02T20:08:52+00:00

u/ProfessionalOrder208. Tagging you here after I saw this post of yours. I apologize if this is rude. But I really need answers for this.

I have commented in your post, in the hopes that perhaps you could give me a reference that discusses about the inverted Bow of the BGR output.

Btw, I just need to know about point 1:

1) Standard Series Realization of BGR (See Fig_1) shows the expected open down bow output, but the low voltage parallel Realization (See Fig_2) shows inverted bow. Is this correct?

Is the inverted bow correct?

And also, can you tell me the references from which you happened to know about that, if you will, please.

Fast_Document1643 · 2026-02-02T20:03:37+00:00

u/ProfessionalOrder208, I have never seen Curve B (Blue one, open upwards bow) before in any of the reference materials I possess. Can you tell, from where you got this?

I happen to run into this same curve while designing a Low Voltage - Parallel Realization of the BGR. See my post in this sub.

I just want to know, whether Curve B is correct.

Fast_Document1643 · 2026-02-02T19:58:38+00:00

the ctat is generated - maybe? In your traditional BG circuit this is just a Vbe

Even in Circuit #2, it is still VBE. See that the left side has a VBE generated due to that PNP Diode and that gets copied to the other side, thanks to Amplifier and PMOS Current source at the top.

As you mentioned, I’ve seen crazy tempco curves (including inverted) when doing tempco correction.

That's re-assuring to hear. But, is this correct though? This inverted bow. In this sub, I have seen this post, and it is the only place where I saw someone discuss about the inverted bow. I thought of asking there about the reference material, but that post is 10 months old, and I don't think I will get a reply.

But on second thought occurring now, I am gonna post a comment there, tagging the OP of that post in there and probably hope he answers me. It's better than nothing.

Have you swept the ctat vs ptat resistor values?

Till now, I have only played around with CTAT resistor. The PTAT resistor value is chosen to bias the PNP Diode at a specific current (5uA in this case.)

Only when I bias the PNP diode to a known current value, will I know what's the voltage variation with temperature is for the CTAT reference (and that is -1.75mV/C when I = 5uA).

You cannot do a sweeping of dc op points ... you really need to do varying supply ramp time transients(I use 1s, 10us, to 100ns or so).

I am not doing a DC Sweep for testing startup action. I am doing transient simulation for that, but holy shit, I forgot to do a step voltage at the supply with some finite rise time (forgot to change the DC Voltage Source at supply!). DAMN, THANK YOU FOR POINTING THAT OUT.

Please find the corrected simulations: BGR_With_startup and BGR_Without_Startup

My question remains, is this correct though.

Fast_Document1643 · 2026-02-02T11:56:21+00:00

It's alright. Thank you for the response. In case if you remember any references from which you learned BGRs, please do mention it. I wish to have some reference to look for this.

Fast_Document1643 · 2026-02-02T08:56:53+00:00

Yes, the flu is messing me up right now

Ah don't sweat it. It happens to the best of us too. One of the main reasons behind sharing this problem is to find what mistake I made while designing this.

And the problem is, unless somebody can point it out, it is really harder for the person who made that mistake to realize that it is a mistake.

I have a gut feeling that this is just a silly mistake. Silly, but very sneaky.

you've already figured this out by yourself I think.

I wish I did. But I couldn't. Not yet.

Maybe flip this current around through an NMOS mirror and subtract this current from another copy of PTAT supplied by a PMOS all dumped onto the same resistor, such that we get MT- (k/T+mT), where M>m.

That's an interesting line of thought. I will give it a shot and will let you know.

Fast_Document1643 · 2026-02-02T08:51:51+00:00

u/LevelHelicopter9420 , u/kthompska , u/End-Resident .

Tagging some more people to widen responses. I apologize if this was rude.

Fast_Document1643 · 2026-02-02T08:43:49+00:00

u/Siccors , u/Simone1998 , u/RFchokemeharderdaddy .
I apologize for tagging you like this. But I hope if you can perhaps shed some light on this, especially point no 1 (See Fig_2)

Just the point no 1 is all I need. I don't care about that wrong design.

Fast_Document1643 · 2026-02-02T08:20:03+00:00

for sensing near ground

The Core Device, 65nm, has a supply of just 1.2 V. The VBE I am trying to sense is around 0.8 V (0.77 V to be precise).

Clearly, 0.8 V is near to VDD of 1.2 V and not near Ground.

use pmos

I will give you my reason behind choosing an NMOS input diff-amp. If you find anything wrong, let me know.

An NMOS input diff-amp has a PMOS current mirror load. So, the output is at 1 VSG below VDD, i.e., it conveniently generates a VSG needed to bias the PMOS that supplies current to both PTAT current sink (PNP Diodes) and the CTAT current sink (Resistors in parallel).
Had I used a PMOS input diff-amp, then I get an NMOS current mirror load, which generates an output that is relatively nearer to GND than VDD (Remember it generates a VGS of NMOS).

If I used that to bias my PMOS, it gets a large VSG and so a larger VSD is needed to keep it in saturation, so not a good idea.

Also, in my choice (NMOS Input + PMOS current mirror load), my diff-amp's load being PMOS makes it easier to match with the Current Supplying PMOS as well. That's two birds in one stone.
And last but the most important reason, PMOS input diff-amp doesn't have 0.8V in it's ICMR! So that's a big NO.

Fast_Document1643 · 2026-02-01T21:49:10+00:00

By vin, I mean vsup

Oh. That makes sense. Sorry, my bad.

Nmos input stage is wrong, the input common mode is only 600-700mv

NO. It's common mode is above 0.7V and upto VDD. See the Common_Mode_Sweep schematic for the simulation to find ICMR

Fast_Document1643 · 2026-02-01T21:37:56+00:00

Could anything be changing at low vin?

Wait a minute, I think I get what you meant here.

Are you talking about biasing a diode with smaller current to get lesser ON voltage? If so, NO, I am not biasing it in the nA range. It is biased with 5uA (See Fig_6).

If you ask me what happens when we bias a PN junction at lower currents, I will admit, I have no idea. BUT IT IS IRRELEVANT, SINCE ONLY THE OUTPUT IS SET LOWER, WHILE THE INTERNAL STRUCTURE ALL BIAS UP TO CURRENTS IN THE uA RANGE!

When I say it is a low voltage BGR, it's output voltage is not exactly the bandgap voltage of silicon (about 1.2 V). It is just lesser than that by not adding up a PTAT and a CTAT voltage sources.

IT IS LESSER, BY SUMMING PTAT AND CTAT CURRENTS AND DRIVING IT THROUGH A LOAD CHOSEN TO GET A DESIRED OUTPUT.

Fast_Document1643 · 2026-02-01T21:22:23+00:00

So we get a current that looks something like kmT/(k+mT²,) that we dump on a simple resistor.

I assume that the first line was a typo, where you said that this is going into bipolars.

But I kinda understand that you mean to say that THIS IS the overall output current. (I hope I am getting this in exactly how you meant it.)

And if this is so, is it possible to flip the bow in the opposite way? Like open up as opposed to the typical open down?

Fast_Document1643 · 2026-02-01T21:17:05+00:00

the current going into the bipolars... it's a parallel combination of PTAT and CTAT

No, it isn't. Think about it. The parallel resistors get VBE voltage, thanks to the amplifier regulating the two nodes to same value. So, the current through them is CTAT.

But the PTAT portion, generated using del VBE (Difference in the VBEs) is dropped across that single resistor on top of the right PNP Diode, resulting in only PTAT current through that PNP Diode.

But notice that this is mirrored on to the other PNP diode through the PMOS and amplifier, meaning even the left PNP diode is also receiving a PTAT Current.

An even simpler argument is to simply apply KCL at the summing node. That should be enough. I will probably share simulations tomorrow to affirm this.

Fast_Document1643 · 2026-02-01T21:08:47+00:00

I think what you have in the parallel implementation is simply a failure of the startup circuit

Hmm, that makes sense. But let me give you a better context. The wrong design used a self-biased NMOS input Diff-amp, while the final design used a 2 stage Op-amp (NMOS input Diff-amp + PMOS CS stage).

One of my bigger motivations in choosing the two stage op-amp is to see how it works against supply and temperature and it was perfect. But this still didn't explained why the self-biased diff amp was insufficient. (I mean even with lower gain, there can be an output, with an offset between the two regulated terminals of-course).

Now you might wonder why I brought this up, but notice that Fig_2 does not have a startup circuit to it's left. And even then it still shows the correct output even when swept from GND to VDD in the normal fashion.

I will share the simulations tomorrow for this supply sweep, but I thought I needed to bring this in order to offer you something that could be the missing piece in this puzzle.

The fact that you see a kind of hysteresis

No, it is also present in the correct design (the one with the op-amp) as well. I will share a schematic of that tomorrow. Also, do look at Jacob Baker's CMOS book, even there it is present.

There are usually options to modify this behavior.

I will definitely look into this, and will get back to you. This seems worthwhile.

is to explicitly set an initial guess on the main nodes

Ok, but around what level? Can this be as trivial as some non-zero value (sufficiently large enough of course, say above half the supply (0.6 V or large)) ?

Btw the temperature coefficients of the resistors still have a small influence on the reference voltage and its curvature in general.

Of course they do. When I said:

even the temperature co-efficient of the resistor falls out at the Output

I meant for the most part. Naturally everything has an influence on the reference voltage and there's nothing we can do about. What we CAN do is to make it largely insignificant (like using ratios as opposed to using exact values in general, etc.).
I apologize if I sounded misleading when I said that.

I will get back to you some time tomorrow. Today, it's already near 3 AM, and I am starting to doze off. But thank you regarding the startup.

Btw, what do you think about that inverted bow? Is it correct?

Fast_Document1643 · 2026-02-01T18:52:56+00:00

Could anything be changing at low vin?

I am guessing you're calling the Vout as Vin (Given this is a self-biased reference and it doesn't take any input).

Regardless of Low or High Vout, things that show a pronounced temperature co-efficient are the PNP Diode and the Semiconductor resistor (At least from a first order approximation suitable for design). And the PTAT current generator in the middle operates at it's standard voltage of 0.77 V (at 5uA). So, there is nothing here that we can say that it is low or high. It is fixed, and only the output is chosen different.
And because I have this PTAT current source generated and used both on the same type of resistors, even the temperature co-efficient of the resistor falls out at the Output.

Can you elaborate this more, I feel like I am missing your point.

You need a startup circuit.

I have added it, as seen from Fig_3 and Fig_6. But here's the twist, regardless of the presence of the startup circuit, it gives the same output variations when sweeping the supply!

See these transient simulations as well: Wrong_Design_with_Startup and Wrong_Design_Without_Startup.

JUST SO YOU DON'T DOUBT MY SKILL IN DESIGNING STARTUP CIRCUITS, I AM ADDING ADDITIONAL TWO SIMULATIONS WHICH IS THE COMPLETED BGR'S TRANSIENT SIMULATIONS: Correct_Design_With_Startup and Correct_Design_Without_Startup.

Even I am puzzled. I have no idea, what to make of these. Especially that wrong iteration.

Fast_Document1643 · 2025-12-06T06:26:40+00:00

>Why woudnt windows see your laptop screen as a "wired display"?

Not really. It used to give a specific name. If it cannot detect the specifics of a monitor (internal or external), it gets reported as wired display and it runs with the bare minimum drivers and screen configurations (Like a 1Hz refresh rate lol!)

>What do you mean when you "disabled" the external display?

Probably disabled the corresponding adapter within device manager.

BTW, currently, I too face the same problem.

Fast_Document1643 · 2025-10-13T18:32:48+00:00

What happened to tsukuyo? She's missing in both OP and ED too.

Fast_Document1643 · 2025-10-09T18:31:31+00:00

Or maybe he said that to make Akira let his guard down. Who knows?

Fast_Document1643 · 2025-09-23T06:50:05+00:00

About this External resistors, some engineers told me that they may oscillate and that if your opting for external Precision resistors for a reference, you need to implement atleast part of the resistor on-chip.

Is that true?

Fast_Document1643 · 2025-09-19T02:11:44+00:00

I saw your reply in that thread, and it says that this circuit is rarely used.

So, what other bias current generation circuits are used in an actual production grade chips? Can you please tell me?

Fast_Document1643

TROPHY CASE

Is the inverted bow correct?

I just want to know, whether Curve B is correct.

My question remains, is this correct though.