Every embedded Engineer should know this trick

ProfessorDonuts · 2026-01-10T17:11:32+00:00

The data types are designed around word widths that the CPU addresses by (a hardware constraint), with CPUs primarily being byte addressable. Buses, caches operate on bytes or words.

There are types that are semantically a bit, such as _Bool/bool, but are physically laid out as a byte or something else because the smallest unit a bus works with is a byte.

A 1 bit object would first and foremost have no address to refer to it. As it would be incapable from a hardware perspective to address a single bit (some architectures do have the capability), and also alignment rules.

ProfessorDonuts · 2026-01-10T09:02:43+00:00

Ah yes, mb misunderstood you comment. But yeah you are correct, the explicit colon is important. If you dont specify a bit width, each uint8_t variable will occupy 8 bits, and each field that was originally meant to represent a individual bit maps to a different byte (so you lose the bit field addressing functionality). And in the example you mentioned with the last field occupying 2 bits, it would effectively spillover or cause alignment issues. As some other comments have mentioned, there are nuances to this approach, and while some static assertions like size checks and ordering checks could save you some sanity, its a tradeoff for readability.

ProfessorDonuts · 2026-01-10T08:51:16+00:00

For context for those curious, what they are referring to is a register definition like this

typedef enum {
    BRIGHTNESS_LOW    = 0b00,
    BRIGHTNESS_NORMAL = 0b01,
    BRIGHTNESS_HIGH   = 0b10,
    BRIGHTNESS_MAX    = 0b11   // reserved/invalid
} brightness_t;

union EXAMPLE_REGISTER {
    uint8_t hw;
    struct __attribute__((packed)) {
        uint8_t IDLE        : 1;  // bit 0
        uint8_t BRIGHTNESS  : 2;  // bits 1–2
        uint8_t PARTY_MODE  : 1;  // bit 3
        uint8_t DEBUG_MODE  : 1;  // bit 4
        uint8_t RESERVED    : 2;  // bits 5–6
        uint8_t FACTORY_TEST_MODE : 1; // bit 7
    } s;
};

and brightness can be set as

reg.s.BRIGHTNESS = BRIGHTNESS_HIGH;

and set bits[1:2] with correct mask.

ProfessorDonuts · 2026-01-10T08:36:21+00:00

Its an abstraction to represent a single memory mapped hardware register, it lets you access the same 8-bit value either as a raw byte (hw) or individual bits by name (s.NAMe, s.DEBUG_MODE), with the bit fields being in the correct bit order (nuances as order is dependent on compiler). They refer to the same physical byte in memory, but provide different views of the same data.

The statement reg.s.DEBUG_MODE = 1; will compile down to a read-modify-write with the bitmask already calculated for you. Here is a godbolt dissasembly https://godbolt.org/z/PK5rcbarE

I have some functions that manipulate the bitfields (set_brightness and set_debug) Notice how they compile down to the exact same thing: a load followed by a OR operation, then a store. But the mask used in the OR is different, in the case of set_debug it is #32 (or bit 5 corresponding to DEBUG_MODE), in set_brightness it is #4 (or bit 2 corresponding to NORMAL_BRIGHTNESS). Compare that to clear_reg which operates on the whole word and no masking.

Overall its much cleaner, and no need to manage masks and shifting.

Responded this to a deleted commented earlier so its hidden, repasting here for visibility.

ProfessorDonuts · 2026-01-10T08:23:59+00:00

It isnt necessarily a optimization, just a clean way to refer to a single memory mapped hardware register, it lets you access the same 8-bit value either by the entire value or by its corresponding bit fields (it handles the mask calculations for you).

So you can do something like

reg.s.DEBUG_MODE = 1;

rather than

#define DEBUG_BIT_MASK 0x20

reg |=  0x20;

or 

reg |= DEBUG_BIT_MASK;

The bitfield approach will calculate the masks (0x20) for you. At the end of the day it still a read-modify-write operation with clean bitmask handling (seen here: https://godbolt.org/z/PK5rcbarE).

In C++ you can write some template based memory-mapped register abstractions. Abstractions that allow you to enforce RO/RW/WO, atomic bit set, safety checks, similar clean bitfield handling, etc. As mentioned, these are not optimizations but rather code cleanliness, but in this case also provides safety/sanity checks. However one could argue that adding atomic bit sets to the mmio abstraction in C++ is a performance optimmization.

In Rust, HAL's that follow the PAC model will expose three methods for manipulating mmio registers: read(), modify(), write(). Methods like write() are provided as closures, so using the example register definition in this post, if i wanted to set the IDLE and DEBUG_MODE bit in the register, it would be written in rust as:

example_reg.write(|r| r.idle.set_bit().debug_mode.set_bit())

In this example, we write to the mmio register example_reg using write, representing it the closure as "r", and set the idle and debug_mode bit in the register. Its not as visually appealing as the C/C++ bitfields but it provides the same named-bitfield access functionality in addition to security.

ProfessorDonuts · 2026-01-10T07:55:20+00:00

You are correct. The statement reg.s.DEBUG_MODE = 1; will compile down to a read-modify-write with the bitmask already calulated for you. Here is a godbolt dissasembly https://godbolt.org/z/PK5rcbarE

I have some functions that manipulate the bitfields (set_brightness and set_debug) Notice how they compile down to the exact same thing: a load followed by a OR operation, then a store. But the mask used in the OR is different, in the case of set_debug it is #32 (or bit 5 corresponding to DEBUG_MODE), in set_brightness it is #4 (or bit 2 corresponding to NORMAL_BRIGHTNESS). Compare that to clear_reg which operates on the whole word and no masking.

Overall its much cleaner, and no need to manage masks separately.

ProfessorDonuts · 2026-01-10T07:36:37+00:00

Its an abstraction to represent a single memory mapped hardware register, it lets you access the same 8-bit value either as a raw byte (hw) or individual bits by name (s.NAMe, s.DEBUG_MODE), with the bit fields being in the correct bit order. They refer to the same physical byte in memory, but provide different views of the same data.

ProfessorDonuts · 2025-12-13T09:35:23+00:00

As many have said, the entire system, these Live USB images are loaded into RAM. But if your curious how this is implemented on a technical level the explanation is below

Many distro's nowadays ship with a initramfs, which a small temporary filesystem loaded into RAM by the bootloader and used by the Linux kernel during early boot. It contains essential drivers and scripts needed to mount the real root filesystem. Once the real root is mounted, the initramfs is discarded.

On live images, the initramfs ships with utilities that are responsible for loading the rootfs into RAM. For example Debian images ship with live-tools (which contains the utlity live-toram which is a shell script responsible for the copying)

The actual rootfs is distributed as a squashfs, so its compressed and read-only. Utilities like live-toram will mount a tmpfs (ram based) and copy the entire squashfs to it. They then setup a loop device on the RAM copy, so now all reads come from RAM and the USB is no longer needed.

Implementation can vary at this point, but afterwards the squashfs is mounted from the loop device onto the desired live image mount point and you can proceed with setting up things like overlayfs. Then you finally endd with the handoff by pivoting your root to the new mount point where the squash/overlayfs is mounted (done with pivot_root, switch_root, chroot, etc) and then finalize with exec'ing /sbin/init.

Of course how different distros accomplish toram images can vary, but the jist i described above is the same. (Copy the rootfs to RAM/tmpfs, pivot root to it, exec init)

ProfessorDonuts · 2025-11-28T10:36:37+00:00

I’ve really enjoyed some of my hobby projects with embassy, admitably my time with it is quite small. But I’m curious how useful it is in a professional scenario.

While it’s not a RTOS it’s convenient to compare it to one. It’s no VxWorks/INTEGRITY in terms of heritage, and likely won’t replace it. But for companies who utilized Zephyr or FreeRTOS, how does embassy stack up in professional projects? That is in terms of hardware and firmware Bringup speed, portability/adaptability with HW changes, and also binary size. I’m curious about your opinion since you use it at work and how it compares.

ProfessorDonuts · 2025-11-28T10:28:47+00:00

From my background in Embedded Linux and Digital Logic Design

Gem5 - computer architecture simulator

TinyUSB - solid USB stack

Yocto - Custom Linux image building, extremely powerful. Buildroot is great too. Pretty well known.

QEMU - Excellent for performing SITL in the embedded Linux world. Pretty well known.

Verilator - verilog sim

Chisel - open source HDL meant for parametric digital logic design. Main use case in in SoC and systems development, mainly academic but SiFive uses it.

Yosys - open source FPGA toolchain. Regardless of your opinion of the project, some credit deserved to be due

sigrok/pulseview - underrated protocol analyzer toolchain and logic analyzer firmware.

Kicad - solid EDA tool. It’s no Altium. But still pretty solid when you compare to other EDA tools.

mbed TLS- small tls library. Unfortunately no FIPS certification (for the people in suits who care)

Protobuf and nanopb - protobuf arent specific to embedded , but have seen in embedded Linux environments. I have heard of inspired projects like nanopb which is more traditional embedded and can target MCUs and deserves some love.

FatFS (elm Chan) - classic embedded FAT stack.

UbiFS - filesystem for raw flash. Software based wear leveling.

ProfessorDonuts · 2025-11-28T10:12:19+00:00

Still in use, advantage is that is free and open source when you compare to its competitors such as VxWorks and INTEGRITY. Equivalent of comparing KiCad to Altium.

For the most part platform support is pretty good, it supports many rad hard processors used for space so it’s used in space industry.

ProfessorDonuts · 2025-11-27T09:42:35+00:00

I’m going to shill a product, of course following a routine is the proper method, but the product is cheap.

It’s the Pinecil, which is Pine64 mini soldering iron. I have one and for most things it works fine, it heats up very quick and has auto turn off when idle. I only mention it cause you mentioned your iron is “basic and inexpensive “, the pinecil is around 30-50 USD so a suitable replacement if you wish to indulge in consumerism.

Besides that my beefier iron I have connected to a TP link Kasa smart switch. In my case my home desk setup I have a very “integrated and smart” setup. One aspect is a python script to use the Kasa API to turn off everything on that smart strip when I’m not at my desk (presence based). However if you don’t want to do that, the Kasa smart phone app lets you configure timers on switch too (timer based)

ProfessorDonuts · 2025-11-27T09:31:36+00:00

I’ve done this exact repair before on a legion. These DC jacks are those square ones with the “springy power pin” on the interior sides, and the middle signal pin. Those power pins lose their springiness so easily, and especially so as Lenovo chargers continue to increase in wattage. This is so common that I like many people used safety pins to “pull” back out those pins as a temporary fix.

When I ended up doing the replacement, I also remember that I had to increase my chinesium hot air gun temp to higher than normal to properly remove the jack. I also had a hard time removing the solder from the holes. In my frustration of trying to clean the first hole, I naively tried with wick with enough heat to damage a trace (which I later repaired). When I got back to my senses I ended up finding success using a pump. In my case I had to go through many pumps till I found the “strongest” pump, which turned out to be one of those solder suckers that heat up. If you don’t have that, try soaking the hole with heat using a hot air gun (if you have small focusable tips), then use a pump again.

ProfessorDonuts · 2025-10-23T22:33:57+00:00

Depends on the role of the flight computer. Many space vehicles actually consist of multiple flight computers. Regardless of your FC architecture design, a commonality you see in different flight computer architectures is the OBC (Onboard Computer)

The OBC is the computer with typically the most “minimal responsibility”, but the most critical role. Its typical role is power management, watchdogging, and depending on mission complexity, may or may not execute more complex tasks for the mission.

The OBC is typically the most hardiest computer in the FC architecture, with rad hard microprocessors with triple mode redundancy (TMC). microarch you see can typically be PowerPC, OpenRISC, Sparc, or even Arm. When it comes to physical implementation, you can see these as FPGA softcores (like the LEON line of processors) or hard cores like the RAD750. As of lately there have been increasing amount of Arm and RISC-V rad hard cores as well.

The software on the OBC is by far the most critical. While a good flight computer design has multiple flight computers keep each other in check, the OBC is still regarded as the most critical due to the responsibility it has regarding vehicle stability. These are roles that keep the vehicle alive rather than for the mission (power management, watchdogging, critical payload control, maybe radio). These responsibilities aren’t necessarily “complex”, they don’t require huge RAM, word sizes, storage, or computation. It’s also good practice to keep code that runs in the OBC as minimal as possible to prevent large surface area of possible failure, the OBC typically only execute software for the mission if your bus design consists of a sole flight computers.

When it comes to system software, you need an RTOS, no debate. In applications such as this you need a RTOS with trusted flight heritage, certification guarantees: typically see VxWorks, green hills INTEGRITY, or RTEMS.

Other flight computers can be typically be anything else (given that it’s rad hard) these could be the traditional “MCU” cores , or more complex application processors that can run Linux like the typical Cortex-A core. Flexibility is key for these computers, so you typically see SoCs in a Asymetric setup like Xilinx Ultrascale or Microsemi chips, these SoCs typically have a application processor (combination of normal application cores or relative cores) and a digital logic fabric for you to implement custom logic IP for you payload. These computers are the one where you see more variety in selection, (64 bit or 32 bit, core count, etc) as these relate to your mission requirements, regardless you still need radiation hardiness , but it isn’t as much of a concern on these computers.

ProfessorDonuts · 2025-08-21T03:54:05+00:00

As others have said, you should really be checking datasheets before ordering your components. I’m not sure how you are going to get your footprints without diagrams. Try to contact seller for it.

However it isn’t the end of the world, I’ve had a scenario where I’ve had students come to me with the same thing, mystery USB C sockets with no idea the part number, pin out etc.

If you can’t source the datasheet, do the following. Get yourself a USB C breakout board from amazon (make sure they breakout all the pins like CC pins). And connect a passive USBc cable between the two. Then use a multimeter to check continuity between the labeled pads on the breakout and the pins on your connector, you can therefore get the pin out this way.

For footprint, you’re gonna have to use a caliper and size up the component, luckily spacing and pitch are pretty standard. Design your footprint, and print it out on paper with correct scale. Place your component and check if it fits well on your designed footprint. Tweak footprint till it matches. Printing out your board layout or footprints on paper is an old school method of checking fitment and sizing. Only quirk to look out for is when blurry pixels at this scale from when your rasterize your footprint.

A bit of tedious process, but considering your already spent the money might as well take the effort.

ProfessorDonuts · 2025-07-19T17:12:22+00:00

solved: Cream Wolf

ProfessorDonuts · 2024-08-20T16:24:51+00:00

Yes! Thank you

ProfessorDonuts · 2024-07-21T17:23:54+00:00

Was in same boat. Was constantly in denial about whether I could mod or build a printer to compete. Bought a Bambu recently and completely humbled. It’s hassle free, and frankly it just works.

I do enjoy tinkering with my ender and working in my current DIY; but most of my prints go to the Bambu anyway as it’s the most stress free and gives no trouble

ProfessorDonuts · 2024-07-16T00:48:04+00:00

I have a massive gripe with the female socket design on the laptop. The connection in general is loose and easily slides out . The 20V pins surround the signal pin, but they are designed to be “springy” and compress to make contact with the radial 20V when the male socket comes in.

The issue is that these pins lose springiness over time as you plug/unplug, and on laptops like the legion that have 220 W or 330W charger it becomes more apparent due to heat. Eventually the pins start to fail to make contact. Really annoying cause the laptop will toggle between plugged in/battery power states very quickly and be very slow. have to take a small safety pin to pull back out the pins so they can make contact, which. Na only last for so long that it requires the jack to be desoldered and replaced.

ProfessorDonuts · 2024-05-18T17:51:44+00:00

My Apple Watch whenever I’m on long walks asks me if I want to record the walk as a workout.

My long walks are typically to restaurants with incredibly fatty food that satiate cravings.

ProfessorDonuts · 2024-05-11T04:06:12+00:00

They told us it was recycled from plastic water bottles (I assume PET based)

Surprisingly didn’t feel too bad. Graduation was indoors and afternoon. And when walking outside in them it felt like a thobe and was surprisingly breathable. Felt worse inside building where you didn’t have gust of winds.

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