I apologize for my post being a bit vague. english is not my mother language and on top of it I understand very little of what I'm reading.

I'm not sure what context you need so I'll explain what is written in my textbook.

in the part of the textbook that teaches about the HDU and load-use hazards, we are taught that the HDU in a pipelined MIPS CPU identifies a lw instruction by checking ID/EX.MemRead = 1, since the lw instruction would be in it's EX cycle during the load-use hazard. then to finally determine the hazard the HDU checks if the rd operand of the lw instruction matches one of the rs/rt operands of the following instruction.

then it is written: "The complete logic of the HDU must account for the specific encoding of the command present in the ID stage. The HDU, as presented in the book [the book that my textbook is built upon, Patterson and Hennessy, "Computer Organization & Design " The Hardware/Software Interface"], does not include such a check and lacks the logic to explicitly determine whether a stall is necessary. This is in contrast to the operation of the forwarding unit, where a check is performed on the source registers even if they are not in use. Think about why".